Semiconductor memory device having a redundancy construction
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorChikayoshi Morishima
Life of this patent
Estimating the term…
Abstract
A semiconductor memory device includes a plurality of column groups (memory blocks M1 to M9), a plurality of column selection circuits and a plurality of read/write circuits disposed in correspondence with the plurality of column groups, a redundancy selection circuit that selects connection to the read/write circuit by shifting the connection, and input/output circuits that selectively connect an input/output node of the redundancy selection circuit with the data input/output line.
Claims8
A semiconductor memory device comprising:
- a memory cell array including m memory blocks (said m is an integer not smaller than 2) each having a plurality of memory cells arranged in a matrix form and n column lines (said n is an integer) connected to the corresponding memory cells;
- m first selection circuits disposed respectively in correspondence with said m memory blocks, each of said m first selection circuits selecting one of said n column lines included in the corresponding one of said m memory blocks;
- m data processing circuits disposed respectively in correspondence with. said m first selection circuits, each of said m data processing circuits including one or both of an amplification circuit for amplifying read data from the corresponding first selection circuit and a write circuit for outputting write data to the corresponding first selection circuit;
- a redundancy selection circuit that includes m first nodes and (m−1) second nodes for respectively giving and receiving data to and from said m data processing circuits and selectively connects (m−1) first nodes with said (m−1) second nodes by shifting connections to exclude one of said m first nodes;
- and
- a second selection circuit that selects one of k second nodes (k≦m−1:
- said k is an integer) for giving and receiving data.
A semiconductor memory device comprising. a memory cell array including m memory blocks (said m is an integer not smaller than 2) each having a plurality of memory cells arranged in a matrix form and n column lines (said n is an integer) connected to the corresponding memory cells;
- m first selection circuits disposed respectively in correspondence with said m memory blocks, each of said m first selection circuits selecting one of said n column lines included in the corresponding one of said m memory blocks;
- a redundancy selection circuit that includes m first nodes and (m−1) second nodes for respectively giving and receiving data to and from said m first selection circuits and selectively connects (m−1) first nodes with said (m−1) second nodes by shifting connections to exclude one of said m first nodes;
- a second selection circuit that selects one of k second nodes (k≦m−1:
- said k is an integer) for giving and receiving data;
- and
- one or both of an amplification circuit for amplifying data output from said second selection circuit and a write circuit for outputting data to said second selection circuit.
Dependencies are inferred from the claim text.