Method for forming gate segments for an integrated circuit

A method for forming a memory device, comprising the steps of:

• forming a shallow trench isolation region with a pad that extends outwardly from active regions of a semiconductor material;
• removing the pad outwardly from the active regions;
• forming a thin insulating layer outwardly from the active regions;
• forming a conductive layer outwardly from the insulating layer;
• planarizing the conductive layer such that a working surface of the conductive layer is substantially coplanar with a surface of the shallow trench isolation region;
• selectively removing portions of the conductive layer and the insulating layer from the active regions to form at least one gate segment in each active region;
• forming source/drain regions in the portions of the active regions not covered by the conductive layer;
• interconnecting the gate segments with word lines;
• and
• selectively coupling bit lines and storage capacitors to the source/drain regions to form an array of cells for the memory device.

A memory device, comprising:

• an array of memory cells interconnected with a plurality of bit lines and word lines, wherein each cell includes an activation device with gates formed as segments that are separated by and self-aligned with a shallow trench isolation region;
• an addressing circuit that is coupled to the array of memory cells to allow selective access to the memory cells;
• and
• wherein the word lines comprise sub-lithographic word lines and the gate segments for the activation devices are formed after the shallow trench isolation region and before the source and drain are doped.