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US 2001/0054926 A1Published application
Synchronous delay circuit
AssigneeNEC Corporation
InventorsKOICHIRO MINAMI, TAKANORI SAEKI, MASASHI NAKAGAWA
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AssigneeNEC Corporation
InventorsKOICHIRO MINAMI, TAKANORI SAEKI, MASASHI NAKAGAWA
Estimating the term…
In a synchronous delay circuit including a first delay circuit array which is constituted of a plurality of cascade-connected delay circuit stages, and a second delay circuit array which is constituted of a plurality of cascade-connected delay circuit stages arranged to have a signal propagating direction opposite to that of the first delay circuit array. Each of the delay circuit stages of the first and second delay circuit arrays includes a CMOS inverter receiving an input signal. A P-channel MOS transistor of the CMOS inverter, a switching P-channel MOS transistor and an additional resistor are connected in series between a power supply line and an output node of the delay circuit stage. An N-channel MOS transistor of the CMOS inverter, a switching N-channel MOS transistor and another additional resistor are connected in series between the ground and the output node of the delay circuit stage. Thus, the current drive capability of each unitary delay circuit is decreased by the additional resistors, so that the delay time per one unitary delay circuit can be increased while minimizing the increase of the jitter. Accordingly, the area of the delay circuit arrays required to obtain a desired delay time can be reduced.
A synchronous delay circuit wherein a unitary delay circuit of a delay circuit array is constituted of a clocked inverter having a current limiting means inserted in series in an output node charging/discharging current path.
A synchronous delay circuit including a delay circuit array constituted of a plurality of cascade-connected unitary delay circuits, each of said plurality of unitary delay circuits including an inverter transistor receiving an input signal, a switching transistor on-off controlled by a control signal, and a current limiting means, which are connected in series in a current path for charging and discharging an output node of said unitary delay circuit.
A synchronous delay circuit including a first delay circuit array which is constituted of a plurality of cascade-connected unitary delay circuits, and a second delay circuit array which is constituted of a plurality of cascade-connected unitary delay circuits arranged to have a signal propagating direction opposite to that of the first delay circuit array, an output node of each of said plurality of cascade-connected unitary delay circuits in said first delay circuit array being connected to an input node of a corresponding unitary delay circuit which is included in said second delay circuit array and which is located at the same position as that unitary delay circuit in said first delay circuit array, counted from an input end of said first delay circuit array and an output end of said second delay circuit array, each of said unitary delay circuits including an inverter having an input connected to said input node of said unitary delay circuit, a switching transistor on-off controlled by a control signal, and a current limiting means, which are connected in series in a current path for charging and discharging an output node of said unitary delay circuit.
Dependencies are inferred from the claim text.