Semiconductor device capable of internally adjusting delayed amount of a clock signal

Abstract

A plurality of internal circuits each include a respective clock adjusting circuit that adjusts the phase of a clock signal given by a clock buffer. Even if a difference in delayed amount of the clock signal is generated by drawing clock interconnections, a different adjustment can be made for each internal circuit, whereby the operation of synchronized circuits respectively included in the plurality of internal circuits can be improved.

Dependencies are inferred from the claim text.