Integrated circuit device having a burn-in mode for which entry into and exit from can be controlled

A method of performing a stress-test of an integrated circuit device in a burn-in oven, said method comprising the steps of:

• monitoring a supply voltage supplied to the integrated circuit device and a temperature of the integrated circuit device;
• detecting when the supply voltage exceeds a predetermined voltage level and when the temperature of the integrated circuit device exceeds a predetermined temperature level;
• and
• entering a burn-in mode of the integrated circuit device when the supply voltage exceeds the predetermined voltage level or when the temperature of the integrated circuit device exceeds a predetermined temperature level.

A method of performing a stress-test mode that is capable of disabling a time-out feature of an integrated circuit memory device in order to facilitate stress testing of the integrated circuit memory device in a burn-in oven, said method comprising the steps of:

• monitoring a supply voltage supplied to the integrated circuit memory device;
• detecting when the supply voltage exceeds a predetermined voltage level;
• entering a burn-in mode of the integrated circuit memory device when the supply voltage exceeds the predetermined voltage level;
• and
• disabling the time-out feature of the integrated circuit memory device upon entry into the burn-in mode by leaving on at least one wordline of a plurality of wordlines of the integrated circuit memory device for the duration of a memory cycle of the integrated circuit memory device.

A method of performing a stress-test mode that is capable of disabling a time-out feature of an integrated circuit memory device in order to facilitate stress testing of the integrated circuit memory device in a burn-in oven, said method comprising the steps of:

• monitoring a supply voltage supplied to the integrated circuit memory device and a temperature of the integrated circuit memory device;
• detecting when the supply voltage exceeds a predetermined voltage level and when the temperature of the integrated circuit memory device exceeds a predetermined temperature level;
• entering a burn-in mode of the integrated circuit memory device when the supply voltage exceeds the predetermined voltage level or when the temperature of the integrated circuit memory device exceeds the predetermined temperature level;
• and
• disabling the time-out feature of the integrated circuit memory device upon entry into the burn-in mode by leaving on a plurality of wordlines of the integrated circuit memory device for the duration of a memory cycle of the integrated circuit memory device.

A method of performing a stress-test of an integrated circuit device in a burn-in oven, said method comprising the steps of:

• monitoring a supply voltage supplied to the integrated circuit device;
• detecting when the supply voltage exceeds a predetermined voltage level;
• entering a burn-in mode of the integrated circuit device when the supply voltage exceeds the predetermined voltage level;
• detecting when the supply voltage drops to a voltage that is equal to or below the predetermined voltage level;
• and
• exiting the burn-in mode when the supply voltage drops to a voltage that is equal to or below the predetermined voltage level.

A method of performing a stress-test of an integrated circuit device in a burn-in oven, said method comprising the steps of:

• monitoring a supply voltage supplied to the integrated circuit device and a temperature of the integrated circuit device;
• detecting when the supply voltage exceeds a predetermined voltage level and when the temperature of the integrated circuit device exceeds a predetermined temperature level;
• entering a burn-in mode of the integrated circuit device when the supply voltage exceeds the predetermined voltage level or when the temperature of the integrated circuit device exceeds the predetermined temperature level;
• detecting when the supply voltage drops to a voltage that is equal to or below the predetermined voltage level and when the temperature of the integrated circuit device drops to a temperature that is equal to or below the predetermined temperature level;
• and
• exiting the burn-in mode when the supply voltage drops to a voltage that is equal to or below the predetermined voltage level or when the temperature of the integrated circuit device drops to a temperature that is equal to or below the predetermined temperature level.

A burn-in stress test mode circuit of an integrated circuit device, comprising:

• a diode stack comprised of a plurality of diodes, wherein the plurality of diodes are serially connected with a first diode of the plurality of diodes connected to a first supply voltage;
• a first transistor having a gate connected to the first supply voltage;
• a second transistor having a gate controlled by a power-on reset signal;
• and
• a first logic element having an input terminal and an output terminal, wherein a node is defined by the electrical connection of the input terminal of the first logic element, a second diode of the plurality of diodes of the diode stack, a second source/drain of the first transistor, and a second source/drain of the second transistor;
• wherein when the first supply voltage of the integrated circuit device exceeds a predetermined voltage level equal to a diode forward bias voltage drop of the diode stack plus a voltage trip point of the first logic element, the integrated circuit device enters a burn-in mode.

A test mode circuit of an integrated circuit device, comprising:

• a plurality of bipolar transistors, each having a collector connected to a first supply voltage, a base, and an emitter, with the emitter of a first bipolar transistor connected to the base of a second bipolar transistor and the base of the first bipolar transistor connected to the first supply voltage;
• a plurality of ETD transistors, each having a first source/drain, a second source/drain, and a gate, with the gate of each ETD transistor being controlled by a signal and with the first source/drain of a first ETD transistor connected to the emitter of the first bipolar transistor and the first source/drain of a second ETD transistor connected to the emitter of the second bipolar transistor;
• a first logic element having an input terminal and an output terminal, wherein a node is defined by the electrical connection of the input terminal of the first logic element, a second source/drain of the second transistor, the emitter of the second bipolar transistor, and the first source/drain of the second ETD transistor;
• wherein the first ETD transistor operates to ensure that the emitter of the first bipolar transistor is Vbe (base-to-emitter voltage) volts lower than the Vb (base voltage) of the first bipolar transistor and wherein the second ETD transistor operates to ensure that the emitter of the second bipolar transistor is Vbe (base-to-emitter voltage) volts lower than the Vb (base voltage) of the second bipolar transistor.