US 2001/0044923 A1 · Memory embedded semiconductor integrated circuit and a method for designing the same

Abstract

The present invention clarifies conditions for the development of a memory embedded semiconductor integrated circuit. The total resource CW of a fabrication technique is defined by utilizing the process number or mask number, for example, required for the fabrication. The unit resource CWU is deduced by dividing the total resource CW with the effective wafer area. The unit resource CWU multiplied by the area of the logic gate forming region is defined as the first effective technique resource CWL, that multiplied by the area of the memory cell forming region is defined as the second effective technique resource CWAM, that multiplied by the area of other regions is defined as the third effective technique resource CWP&IO. The fabrication and/or design are compared by using the first to the third effective technique resources CWU, CWL and CWAM, those suitable to the required scales of the memory and the logic circuit are selected.

Claims14

Dependent claims

A method for designing a memory embedded semiconductor integrated circuit having a first region where logic gates are formed, a second region where memory cells are formed, and a third region including all other regions but the first region and the second region, said method comprising the steps of:

defining a total resource of a fabrication technique by utilizing various numerical values represented by the process number or mask number required for fabricating the memory embedded semiconductor integrated circuit;
deducing a unit resource by dividing said total resource by the effective wafer area;
defining a first effective technique resource, a second effective technique resource, and a third effective technique resource by multiplying said unit resource by the area of the first region, the area of said second region, and the area of said third region, respectively;
comparing a plurality of techniques concerning fabrication and/or design by using the first to the third effective technique resources obtained as these techniques are employed;
and
selecting from said plurality of techniques those suitable to the required scales of the memory and the logic circuit.

3 more elements

A memory embedded semiconductor integrated circuit comprising:

a first region wherein a logic gate array is formed;
a second region wherein a memory cell array is formed;
and
a third region other than the first region and the second region, and wherein
said circuit fulfills the condition of satisfying the equation (1), that is,
5 [ CWU ⁡ ( n ) × SPLG ⁡ ( n ) - CWU ⁡ ( i ) × SPLG ⁡ ( i ) ] × NLG + [ CWU ⁡ ( n ) × SPB ⁡ ( n ) - CWU ⁡ ( i ) × SPB ⁡ ( i ) ] × NMB + [ CWU ⁡ ( n ) × SP & ⁢ IO ⁡ ( n ) - CWU ⁡ ( i ) × SP & ⁢ IO ⁡ ( i ) ] < 0 ( 1 )
where,
CWU(n) denotes the unit resource, which is defined as the division by the effective wafer area of the fabrication technique total resource represented by the process number and/or the mask number required for fabricating said memory embedded semiconductor integrated circuit using technique N that is under investigation,
CWU(i) denotes the unit resource when using for fabrication the ith technique I among a number of m (m:
a natural number) techniques that are for comparison,
SPLG(n) is the area per logic gate of said first region as technique N is employed,
SPLG(i) is the area per logic gate of said first region as technique I is employed,
SPB(n) is the area per memory bit of said second region as technique N is employed,
SPB(i) is the area per memory bit of said second region as technique I is employed,
SP&IO(n) is the area of said third region as technique N is employed,
SP&IO(i) is the area of said third region as technique I is employed,
NGL is the total number of the logic gates in said first region, and
NMB is the total number of the memory bits in said second region.

15 more elements

Dependencies are inferred from the claim text.

Memory embedded semiconductor integrated circuit and a method for designing the same

Life of this patent

Memory embedded semiconductor integrated circuit and a method for designing the same

Life of this patent

Abstract

Claims14