Method of fabricating memory cell with vertical transistor

A method of fabricating memory cell with vertical transistor, comprising:

• providing a semiconductor substrate;
• forming a pad layer on a surface of the substrate;
• forming a deep trench in the substrate;
• forming a trench capacitor at the lower portion of the deep trench;
• forming a collar oxide layer on sidewalls the upper portion of the deep trench that is above trench capacitor;
• forming a first conductive layer above the trench capacitor and fills the deep trench;
• partially removing the first conductive layer to a first predetermined depth in the deep trench to form a first opening;
• removing a part of the collar oxide layer until the top surface of the collar oxide layer is lower than the top surface of the first conductive layer;
• forming a second conductive layer to fill the first opening;
• defining the pad layer, the substrate, the second conductive layer, the collar oxide layer and the first conductive layer to a second predetermined depth to form a second opening;
• forming a first insulating layer to fill the second opening and form a shallow trench isolation;
• partially removing the second conductive layer to a third predetermined depth to form a buried strap and a third opening;
• forming an insulating spacers on sidewalls of the third opening;
• forming a second insulating layer on the buried strap;
• removing the pad layer and the insulating spacer;
• forming a third insulating layer on the exposed surface of the substrate and the sidewalls of the third opening;
• forming a well at the upper portion of the substrate;
• removing the third insulating layer and forming a fourth insulating layer on the well;
• removing the fourth insulating layer on the top surface of the well to form a gate oxide;
• sequentially forming a third conductive layer and a fourth conductive layer to fill the third opening and cover the surface of both the substrate and the shallow trench isolation;
• defining the third conductive layer and the fourth conductive layer to form a gate;
• forming source and drain regions;
• and
• forming gate spacers.