Method of fabricating memory cell

A method of fabricating memory cell with vertical transistor, comprising:

• providing a semiconductor substrate;
• forming a pad layer on the surface of the substrate;
• forming a deep trench in the substrate;
• forming a trench capacitor at the lower portion of the deep trench;
• forming a collar oxide layer on sidewalls of the upper portion of said deep trench that is above said trench capacitor;
• forming a first conductive layer above said trench capacitor and fills the deep trench;
• etching said first conductive layer to a first predetermined depth in said deep trench to form a first opening;
• removing a portion of said collar oxide layer above said first conductive layer;
• forming a second conductive layer to fill said first opening;
• etching back said second conductive layer to a second predetermined depth to form a second opening, in which the residual second conductive layer forms a buried strap;
• forming a first insulating layer conformally over said pad layer and the sidewalls and bottom of said second opening;
• forming a second masking layer over said first insulating layer so that said second masking layer fills the inner space of said second opening;
• performing a planarization process to remove portions of said second masking layer and said first insulating layer above said pad layer;
• defining said pad layer, said substrate, said second masking layer, said first insulating layer, said collar oxide layer and said first conductive layer to a third predetermined depth to form a third opening;
• forming a second insulating layer to fill said third opening;
• removing a portion of said second insulating layer to form a Shallow Trench Isolation;
• removing a portion of said second masking layer to a fourth predetermined depth and forming a fourth opening;
• removing said pad layer to expose said surface of the substrate;
• forming a third insulating layer on the exposed surface of said substrate and the surface of said second masking layer in said fourth opening;
• forming a well at the upper portion of the substrate;
• removing said third insulating layer and said first insulating layer covering said substrate in said fourth opening while said residual first insulating layer and said second masking layer are remained on said buried strap;
• removing said second masking layer on the bottom of said fourth opening;
• forming a fourth insulating layer on the surface of said substrate and on the sidewalls of the fourth opening;
• removing the portion of said fourth insulating layer on the top surface of said substrate to form a gate oxide;
• sequentially forming a third conductive layer and a fourth conductive layer to fill the fourth opening and cover the surface of both the substrate and the shallow trench isolation;
• defining the third conductive layer and the fourth conductive layer to form a gate;
• forming source and drain regions;
• and
• forming gate spacers.