Method for reducing single bit data loss in a memory circuit
AssigneeMicron Technology, Inc.
InventorALAN R. REINBERG
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Abstract
The present invention includes a method for reducing random bit data loss in a memory circuit. The method comprises a semiconductor layer that has a surface. The semiconductor layer is exposed at an elevated temperature to an atmosphere comprising deuterium thereby forming a film on the semiconductor layer comprising deuterium. A memory circuit is fabricated on or within the semiconductor layer.
Claims38
A method for reducing random single bit data loss in a memory circuit comprising:
- providing a semiconductor layer having a surface;
- heating the layer in an atmosphere comprising a Hydrogen isotope;
- and
- fabricating a memory circuit using the semiconductor layer.
An annealing atmosphere for annealing a semiconductor device with a FLASH memory comprising Hydrogen isotope and or a compound that comprises Hydrogen isotope.
A memory circuit, comprising:
- a main body comprising silicon;
- a memory cell disposed on and within the main body;
- a gate region proximal to the memory cell disposed on and within the main body;
- and
- a film disposed on or within the gate region, adjacent to the gate region or under the gate region, wherein the film comprises Hydrogen isotope.
A method of forming a non-volatile electrically alterable semiconductor memory cell comprising:
- providing a silicon substrate;
- fabricating a field oxide region and a channel region over or within the silicon substrate;
- growing an oxide over the channel region in an atmosphere enriched in Hydrogen isotope;
- fabricating at least one gate member;
- and
- passivating the memory cell in an atmosphere that comprises Hydrogen isotope.
A tunneling oxide component of a non-volatile, electrically alterable semiconductor memory cell, comprising Hydrogen isotope.
A thermal oxide component of a non-volatile, electrically alterable semiconductor memory cell, comprising Hydrogen isotope.
A method for passivating a non-volatile, electrically alterable semiconductor memory cell, comprising:
- providing a non-volatile, electrically alterable semiconductor memory cell;
- and
- exposing the memory cell to an atmosphere that comprises Hydrogen isotope.
A method for overlaying source and drain regions of a non-volatile, electrically alterable semiconductor memory cell with a thermal oxide layer, comprising:
- providing a silicon substrate;
- defining source and drain regions;
- and
- growing the thermal oxide layer over the source and drain regions in an atmosphere that comprises Hydrogen isotope.
Dependencies are inferred from the claim text.