Method for dividing the frequency of a clock signal and frequency divider circuit for implementing the method
AssigneeSiemens Aktiengesellschaft
InventorBirgit Stehle
Life of this patent
Estimating the term…
Abstract
To divide a clock signal, a clock pulse counter counting clock pulses of the clock signal is in each case alternately reset after passing through different count differences. In this process, a first signal and a second signal is formed, the logic state of which is in each case changed with the presence of a first or, respectively, second predetermined count of the clock pulse counter by a rising or, respectively, falling clock signal edge. A divided output clock signal is then generated by a logical operation on the first and the second signal.
Claims19
A method for dividing the frequency of a clock signal, comprising:
- counting clock pulses of the clock signal by a clock pulse counter;
- alternately resetting the clock pulse counter after passing through a first count difference and after passing through a different, second count difference;
- forming a first signal, the logic state of which is changed by a rising clock signal edge when the clock pulse counter has a predetermined first count;
- forming a second signal, the logic state of which is changed by a falling clock signal edge when the clock pulse counter has a predetermined second count;
- and
- generating a divided output clock signal by a logical operation on the first signal and the second signal.
A frequency divider circuit for dividing a clock signal, comprising
- a clock pulse counter for counting the clock pulses of the clock signal;
- a reset circuit for resetting the clock pulse counter after it has in each case alternately passed through a first count difference and a different second count difference;
- a signal generating circuit for forming a first signal with a logic state which changes with the presence of a predetermined first count of the clock pulse counter and a rising clock signal edge, and
- for forming a second signal with a logic state which changes with the presence of a predetermined second count of the clock pulse counter and a falling clock signal edge;
- and
- a logical gate circuit for logically combining the first signal and the second signal to form a divided output clock signal to be output.
Dependencies are inferred from the claim text.