Semiconductor memory device and synchronous memory

A semiconductor memory device for storing data comprising:

• a data input circuit for receiving the data;
• a mask signal input circuit connected to the data input circuit for receiving a mask signal used to mask the data and providing the mask signal to the data input circuit;
• and
• an input control circuit connected to the mask signal input circuit for generating an activation signal that activates the mask signal input circuit and providing the activation signal to the mask signal input circuit, wherein the input control circuit generates the activation signal based on at least one of a plurality of mode setting signals and a latency determination signal, the mode setting signal being used to activate the mask signal input circuit and selectively set one of a plurality of operation modes of the semiconductor memory device, and the latency determination signal having a level corresponding to latency information.

A synchronous memory for storing data and reading stored data based on a clock signal comprising:

• a data output circuit for receiving and outputting the stored data based on the clock signal;
• a mask signal input circuit connected to the data output circuit for receiving a mask signal used to mask the data output from the data output circuit and providing the mask signal to the data output circuit;
• and
• an input control circuit connected to the mask signal input circuit for generating an activation signal that activates the mask signal input circuit and providing the activation signal to the mask signal input circuit, wherein the input control circuit generates the activation signal based on at least one of a plurality of mode setting signals and a latency determination signal, the mode setting signal being used to activate the mask signal input circuit and selectively set one of a plurality of operation modes of the synchronous memory, and the latency determination signal having a level corresponding to latency information.

A synchronous memory for storing data and reading stored data based on a clock signal comprising:

• a data input circuit for receiving the data;
• a mask signal input circuit connected to the data input circuit for receiving a mask signal used to mask the data and providing the mask signal to the data input circuit;
• and
• an input control circuit connected to the mask signal input circuit for generating an activation signal that activates the mask signal input circuit and providing the activation signal to the mask signal input circuit, wherein the input control circuit generates the activation signal based on at least one of a plurality of mode setting signals and a latency determination signal, the mode setting signal being used to activate the mask signal input circuit and selectively set one of a plurality of operation modes of the synchronous memory, and the latency determination signal having a level corresponding to latency information.