Layout structure and method of a column path of a semiconductor memory device

A method for constructing a write column path layout structure of a semiconductor memory device comprising:

• setting up the first and second transistors including bit line pairs respectively connected to a plurality of memory cells, section data line pairs being arranged in parallel to the bit line pairs, first contact lines of a metal conductivity layer arranged under the bit line pairs to contact the bit line pairs through a first contact, second contact lines of a metal conductivity layer being arranged under the bit line pairs to contact the section data line pairs through a second contact, gates and drains and sources having their active regions in perpendicular to the longitudinal direction of the bit line pairs;
• connecting the drains of the first and second transistors with the bit line pairs by making the drains of the first and second transistors respectively in contact with the first contact lines through the first contact, wherein the first contact lines and the bit line pairs cross each other;
• connecting the sources of the first and second transistors with the section data line pairs by positioning the sources of the first and second transistors to be in the shared arrangement of transistors of directly neighboring memory cells, to be in contact with the second contact lines and making a contact through the second contact, wherein the second contact lines and the section data line pairs cross each other;
• and
• arranging the first transistors for bit lines and the second transistors for bit line bars within an area occupied by a predetermined total number of memory cells in a top/bottom sequence.