Analog to digital converter with encoder circuit and testing method therefor

An encoder for encoding a thermometer code, comprising:

• an encoder circuit for detecting a logical boundary of the thermometer code to produce a Gray code signal, wherein the Gray code signal comprises a lower order bit and an upper order bit, and a particular relationship is set between the lower order bit and the upper order bit when the Gray code signal is error free;
• an error detector circuit, coupled to the encoder circuit, for detecting whether the particular relationship is satisfied and generating an error bit signal when the particular relationship is not satisfied;
• an error correction circuit, coupled to the encoder circuit and the error detector circuit, for correcting an error bit of the Gray code signal in response to the error bit signal and generating a corrected bit signal;
• and
• a Gray to binary converter circuit connected to the error correction circuit for converting the Gray code signal including the corrected bit signal into a binary code signal.

An encoder for encoding a thermometer code, comprising:

• an encoder circuit for detecting a logical boundary of the thermometer code to produce a Gray code signal including an upper bit and decomposed lower order bits regarding a lower order bit of the Gray code, wherein a particular relationship is set between the upper bit and the decomposed lower order bits when the Gray code in error free;
• an error detector circuit, coupled to the encoder circuit, for detecting whether the particular relationship between the lower order and upper order bits is satisfied and generating an error bit signal when the particular relationship is not satisfied;
• and
• a Gray to binary converter circuit, coupled to the encoder circuit and the error detector circuit, for correcting an error bit of the Gray code signal in response to the error bit signal and converting the Gray code signal including corrected bit signal into a binary code signal.

An A/D converter, comprising:

• a plurality of comparators for receiving and comparing an analog input voltage with reference voltages different from each other and producing a thermometer code based upon the comparison results;
• a logical boundary detector, coupled to the comparators, for detecting a logical boundary of the thermometer code and outputting a logical boundary detection signal;
• and
• an encoder coupled to the logical boundary detector for receiving the logical boundary detection signal and generating a binary code signal, wherein the encoder includes:
• an encoder circuit for receiving the logical boundary detection signal to produce a Gray code signal, wherein the Gray code signal comprises a lower order bit and an upper order bit, and a particular relationship is set between the lower order bit and the upper order bit when an error code bit is not included in the Gray code;
• an error detector circuit coupled to the encoder circuit for detecting whether the particular relationship between the lower order and upper order bits is set and generating an error bit signal when the particular relationship is not satisfied;
• an error correction circuit, coupled to the encoder circuit and the error detector circuit, for correcting an error bit of the Gray code signal in response to the error bit signal and generating a corrected bit signal;
• and
• a Gray to binary converter circuit for converting the Gray code signal including the corrected bit signal into a binary code signal.

An error correction method for an encoded signal including a thermometer code, comprising the steps of:

• detecting a logical boundary of the thermometer code;
• producing, based on the detected logical boundary, a Gray code including a lower order bit and an upper order bit, wherein a particular relationship is set between the lower order bit and the upper order bit when an error code bit is not included in the Gray code;
• determining whether the particular relationship is satisfied;
• and
• correcting an error code bit included in the Gray code using a predetermined error code processing procedure when the particular relationship is not satisfied.

An error correction method for an encoded signal including a thermometer code, comprising the steps of:

• detecting a logical boundary of the thermometer code;
• producing, based on the detected logical boundary, a Gray code including a lower order bit and an upper order bit;
• dividing the lower order bit into a front lower order bit of a logical target and a back lower order bit of a non-logical target;
• decomposing the front lower order bit into decomposed front lower order bits and decomposing the back lower order bit into decomposed back lower bits, so that a particular relationship is set between the decomposed front and back lower order bits and the upper order bit when an error code bit is not included in the Gray code;
• determining whether the particular relationship is satisfied;
• and
• correcting an error code bit included in the Gray code using a predetermined error code processing procedure when the particular relationship is not satisfied.

A recording medium having recorded thereon a computer readable program code for correcting an error code included in a Gray code, the Gray code having a lower order bit and an upper order bit, wherein the lower order bit includes a logical target lower order bit and a non-logical target lower order bit, the computer readable program performing the steps of:

• decomposing at least one of the logical and non-logical target lower order bits to generate decomposed Gray code;
• comparing the decomposed Gray code with the upper order bit to detect an error code bit;
• and
• correcting the error code bit included in the Gray code.

A recording medium having recorded thereon a computer readable program code for correcting an error code included in a Gray code, the Gray code having a lower order bit and an upper order bit, wherein the lower order bit includes a logical target lower order bit and a non-logical target lower order bit, the computer readable program performing the steps of:

• decomposing at least one of the logical and non-logical target lower order bits to generate decomposed lower order bits;
• comparing the decomposed lower order bits with the upper order bit to detect an error code bit;
• and
• correcting the error code bit included in the Gray code.

A recording medium having recorded thereon a computer readable program code for correcting an error code included in a Gray code, the Gray code having a lower order bit and an upper order bit, wherein the lower order bit includes a logical target lower order bit and a non-logical target lower order bit, the computer readable program performing the steps of:

• decomposing at least one of the logical and non-logical target lower order bits to generate decomposed lower order bits;
• comparing the decomposed lower order bits with the upper order bit to detect an error code bit;
• correcting the error code bit included in the Gray code by inverting the error code bit;
• and
• converting the Gray code including the corrected code bit into a binary code.

A testing method for an A/D converter, comprising the steps of:

• detecting a logical boundary of a thermometer code to produce a Gray code including a lower order bit and an upper order bit which have a particular relationship;
• determining whether the particular relationship is satisfied;
• generating an error signal when the particular relationship is not satisfied;
• and
• detecting whether an error code is included in the thermometer code based on the error signal.

A testing method for an A/D converter operating in accordance with a sampling clock signal, comprising the steps of:

• producing an analog signal having a phase which varies successively with respect to the sampling clock signal;
• sampling the analog signal in accordance with the sampling clock signal to generate a digital signal using the A/D convertor;
• and
• evaluating the digital signal.

A testing method for an A/D converter operating in accordance with a sampling clock signal, comprising the steps of:

• producing an analog signal having one of a DC level and amplitude which varies successively with respect to the sampling clock signal;
• sampling the analog signal in accordance with the sampling clock signal to generate a digital signal using the A/D converter;
• and
• evaluating the digital signal.

A testing method for an A/D converter converting an analog signal to a digital signal, comprising the steps of:

• producing a sampling clock signal having a phase which varies successively with respect to the analog signal;
• sampling the analog signal in accordance with the sampling clock signal to generate the digital signal using the A/D converter;
• and
• evaluating the digital signal.

A testing method for an A/D converter comprising the steps of:

• producing a sampling clock signal having one of a DC level and amplitude which varies successively with respect to an analog signal;
• sampling the analog signal in accordance with the sampling clock signal to generate a digital signal using the A/D converter;
• and
• evaluating the digital signal.

A testing method for an A/D converter operating in accordance with a sampling clock signal, comprising the steps of:

• producing an analog signal from the sampling clock signal;
• producing a comparison reference voltage which successively varies;
• providing the analog signal and the comparison reference voltage to the A/D converter;
• sampling the analog signal in accordance with the sampling clock signal to generate a digital signal based on the sampled analog signal and the comparison reference voltage using the A/D converter;
• and
• evaluating the digital signal.

A semiconductor device, comprising:

• an analog signal production circuit for receiving a sampling clock signal and producing an analog signal;
• a comparison reference voltage production circuit for producing a comparison reference voltage which successively varies;
• and
• an A/D converter for receiving the analog signal and the comparison reference voltage and sampling the analog signal in accordance with the sampling clock signal, the A/D converter further generating a digital signal based on the sampled analog signal and the comparison reference voltage.