Internal clock signal generating circuit permitting rapid phase lock

Abstract

An internal clock signal generating circuit according to the present invention is composed of a minute delay stage that can change a delay amount minutely and a delay stage that changes its delay amount by a larger amount. The minute delay stage responds to a control signal output from a control circuit and fine adjusts its delay amount. The delay stage includes a plurality of fixed delay circuits that realize a relatively large delay amount, respectively. The fixed delay circuit to be connected to the minute delay stage is selected based on the control of the control circuit. Accordingly, the internal clock signal generating circuit is applicable to a wide range of frequencies, occupying a very small space.

Dependencies are inferred from the claim text.