Semiconductor integrated circuit, delay-locked loop having the same circuit, self-synchronizing pipeline type system, voltage-controlled oscillator, and phase-locked loop

A delay-locked loop comprising:

• a semiconductor integrated circuit comprising a circuit unit, said circuit unit comprising
• an NMOS transistor and a PMOS transistor connected to each other between gate terminals thereof and between drain terminals thereof, and
• first and second capacitor means connected in parallel at one terminal of each capacitor means to the gate electrodes of the NMOS transistor and the PMOS transistor connected to each other, the other terminal of the first capacitor means being an input terminal and the other terminal of the second capacitor means being a control terminal,
• wherein a source terminal of said NMOS transistor is a ground terminal, a source terminal of said PMOS transistor is a power-supply terminal, and the drain terminals of the NMOS transistor and the PMOS transistor connected to each other are an output terminal;
• a phase comparator to which a reference clock and an output from the output terminal of said semiconductor integrated circuit are input;
• and
• a low-pass filter to which a phase difference resulting from comparison in said phase comparator is input;
• wherein an output of said lower-pass filter is input to the control terminal of said semiconductor integrated circuit.

A self-synchronizing pipeline type system comprising:

• a semiconductor integrated circuit comprising a circuit unit, said circuit unit comprising
• an NMOS transistor and a PMOS transistor connected to each other between gate terminals thereof and between drain terminals thereof, and
• first and second capacitor means connected in parallel at one terminal of each capacitor means to the gate electrodes of the NMOS transistor and the PMOS transistor connected to each other, the other terminal of the first capacitor means being an input terminal and the other terminal of the second capacitor means being a control terminal,
• wherein a source terminal of said NMOS transistor is a ground terminal, a source terminal of said PMOS transistor is a power-supply terminal, and the drain terminals of the NMOS transistor and the PMOS transistor connected to each other are an output terminal;
• an input latch;
• a signal processing logic circuit;
• an output latch;
• and
• first and second handshake circuits;
• wherein digital input data and an output from the first handshake circuit are input to said input latch, data from said input latch is input to said signal processing logic circuit, an output from said signal processing logic circuit and an output from said second handshake circuit are input to the output latch, a clock signal output from the first handshake circuit is input to the control terminal of said semiconductor integrated circuit, and an output from said semiconductor integrated circuit is input to the second handshake circuit.

A voltage-controlled oscillator comprising:

• a plurality of circuit units, each said circuit unit comprising
• an NMOS transistor and a PMOS transistor connected to each other between gate terminals thereof and between drain terminals thereof, and
• first and second capacitor means connected in parallel at one terminal of each capacitor means to the gate electrodes of the NMOS transistor and the PMOS transistor connected to each other, the other terminal of the first capacitor means being an input terminal and the other terminal of the second capacitor means being a control terminal,
• wherein a source terminal of said NMOS transistor is a ground terminal, a source terminal of said PMOS transistor is a power-supply terminal, and the drain terminals of the NMOS transistor and the PMOS transistor connected to each other are an output terminal;
• wherein an output terminal of each said circuit unit is connected to an input terminal of a circuit unit of a next stage, an input terminal of the circuit unit of the first stage is connected to an output terminal of the circuit unit of the final stage, the control terminals of the circuit units of the first stage and the final stage are connected to each other, and the control terminals of the circuit units except for the first stage and the final stage are connected to each other.

A phase-locked loop comprising:

• a voltage-controlled oscillator comprising
• a plurality of circuit units, each said circuit unit comprising
• an NMOS transistor and a PMOS transistor connected to each other between gate terminals thereof and between drain terminals thereof, and
• first and second capacitor means connected in parallel at one terminal of each capacitor means to the gate electrodes of the NMOS transistor and the PMOS transistor connected to each other, the other terminal of the first capacitor means being an input terminal and the other terminal of the second capacitor means being a control terminal,
• wherein a source terminal of said NMOS transistor is a ground terminal, a source terminal of said PMOS transistor is a power-supply terminal, and the drain terminals of the NMOS transistor and the PMOS transistor connected to each other are an output terminal, and
• wherein an output terminal of each said circuit unit is connected to an input terminal of a circuit unit of a next stage, an input terminal of the circuit unit of the first stage is connected to an output terminal of the circuit unit of the final stage, the control terminals of the circuit units of the first stage and the final stage are connected to each other, and the control terminals of the circuit units except for the first stage and the final stage are connected to each other;
• a phase comparator to which a signal of a frequency fO is input;
• and
• a low-pass filter to which an output from said phase comparator is input;
• wherein an output from said low-pass filter is input to the control terminal of said voltage-controlled oscillator and an output from said voltage-controlled oscillator is input to said phase comparator.