Semiconductor memory device
AssigneeSeiko Epson Corporation
InventorsTakashi Kumagai, Masahiro Takeuchi, Satoru Kodaira, Takafumi Noda
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Abstract
The drain of a drive transistor Q3 and the drain of a load transistor Q5 are connected by a first drain-drain contact layer. The drain of a drive transistor Q4 and the drain of a load transistor Q6 are connected by a second drain-drain contact layer. The gate electrodes of the drive transistor Q3 and the load transistor Q5 (a first gate electrode layer) are connected to the second drain-drain contact layer by a first drain-gate contact layer. The gate electrodes of the drive transistor Q4 and the load transistor Q6 (a second gate electrode layer) are connected to the first drain-drain contact layer by the second drain-gate contact layer.
Claims20
A semiconductor memory device which stores data by a flip-flop configured of a first inverter and a second inverter, the semiconductor memory device comprising:
- a first gate electrode layer and a second gate electrode layer;
- a first drain-drain contact layer and a second drain-drain contact layer;
- and
- a first drain-gate contact layer and a second drain-gate contact layer,
- wherein each of the first and second inverters comprises a load transistor and a drive transistor,
- wherein each of the first and second gate electrode layers comprises gate electrodes of the load transistor and the drive transistor,
- wherein each of the first and second drain-drain contact layers connects a drain of the load transistor to a drain of the drive transistor,
- wherein the first and second gate electrode layers are positioned between the first drain-drain contact layer and the second drain-drain contact layer,
- wherein the first drain-gate contact layer connects the first drain-drain contact layer to the second gate electrode layer,
- wherein the second drain-gate contact layer connects the second drain-drain contact layer to the first gate electrode layer, and
- wherein the first and second drain-gate contact layers, the first and second drain-drain contact layers, and the first and second gate electrode layers are each formed in different layers.
A semiconductor memory device having a memory cell that includes a plurality of transfer transistors and a flip-flop configured of a first inverter and a second inverter, the semiconductor memory device comprising:
- a first gate electrode layer and a second gate electrode layer;
- a first drain-drain contact layer and a second drain-drain contact layer;
- and
- a first drain-gate contact layer and a second drain-gate contact layer,
- wherein each of the first and second inverters comprises a load transistor and a drive transistor,
- wherein each of the first and second gate electrode layers comprises gate electrodes of the load transistor and the drive transistor,
- wherein each of the first and second drain-drain contact layers connects a drain of the load transistor to a drain of the drive transistor,
- wherein the first and second gate electrode layers are positioned between the first drain-drain contact layer and the second drain-drain contact layer,
- wherein the first drain-gate contact layer connects the first drain-drain contact layer to the second gate electrode layer,
- wherein the second drain-gate contact layer connects the second drain-drain contact layer to the first gate electrode layer, and
- wherein the first and second drain-gate contact layers, the first and second drain-drain contact layers, and the first and second gate electrode layers are each formed in different layers.
Dependencies are inferred from the claim text.