Semiconductor device and manufacturing method thereof
OwnerManabu Tomita, Takashi Hayakawa +5inventors
InventorsManabu Tomita, Takashi Hayakawa, Masayuki Yasuda, Michio Nishimura, Minoru Ohtsuka, Masayuki Kojima, Kazuo Yamazaki
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Abstract
The invention relates to a method for forming connection holes reliably by making contact resistance low and uniform in semiconductor devices. Insulating layer 3, that includes SOG layer 7, is plasma etched using an etching gas with a small quantity of a gas with a low C/F ratio, such as CHF3, mixed with a gas with a high C/F ratio, such as C4F8/Ar/O2 at a ratio of 1:3.
Claims9
Semiconductor device manufacturing method that includes a process where an insulating layer on a semiconductor substrate is etched using a mixed gas of multiple types of fluorocarbon gases that have different ratios of carbon atoms to fluorine atoms (hereafter called C/F ratio).
Semiconductor device in which a lower conducting layer that has a titanium nitride layer on its surface is formed on the semiconductor substrate as an electrode or wiring, a connection hole is formed in an insulating layer that includes a spin-on glass layer to cover this lower conducting layer, and an upper conducting layer that is connected to the aforementioned lower electrode layer is formed in the aforementioned connection hole as an electrode or wiring, where the aforementioned connection hole is formed to the center position of the thickness of the aforementioned titanium nitride layer through the aforementioned insulating layer.
Dependencies are inferred from the claim text.