Isolated junction structure and method of manufacture
AssigneeIntel Corporation
InventorCHULIN LIANG
Life of this patent
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Abstract
A MOSFET structure in which the channel region is contiguous with the semiconductor substrate while the source and drain junctions are substantially isolated from the substrate, includes a dielectric volume formed adjacent and subjacent to portions of the source and drain regions. In a further aspect of the invention, a process for forming an isolated junction in a bulk semiconductor includes forming a dielectric volume adjacent and subjacent to portions of the source and drain regions.
Claims26
A MOSFET structure comprising:
- a semiconductor substrate having pedestals integrally formed on a surface of the semiconductor substrate, the pedestals having a top portion and a stem portion;
- a gate insulator layer superjacent the top portion of the pedestal;
- and
- a gate electrode overlying the gate insulator layer.
A method of forming an isolated junction field effect transistor comprising:
- a) depositing a layer of trench masking material on a surface of a semiconductor substrate;
- b) patterning the layer of trench masking material to expose portions of the semiconductor substrate;
- c) etching the semiconductor substrate to form at least one trench, wherein each of the at least one trenches has a bottom surface and a side surface;
- d) depositing a conformal layer of spacer material;
- e) forming spacers adjacent to the trench side surfaces by anisotropically etching the spacer material until the semiconductor substrate at the bottom surface of the at least one trench is exposed;
- f) isotropically etching the exposed semiconductor substrate;
- g) filling each of the at least one trenches with at least one dielectric material;
- h) forming a gate insulator layer;
- i) forming a gate electrode over the gate insulator layer;
- and
- j) implanting impurities to form a source and a drain region.
A method of forming an isolated junction comprising:
- a) lining vertical sidewalls of a trench formed in a surface of a semiconductor substrate with a spacer material;
- b) isotropically etching the trench with an etchant that is more selective for the semiconductor substrate than for the spacer material, to form an undercut portion of the trench;
- c) removing the remaining spacer material;
- d) oxidizing inner surface of the trench;
- e) forming air gaps in the undercut portion of the trench by partially filling trench with insulation material;
- and
- f) implanting impurities into a portion of the semiconductor material that overlies the undercut portion of the trench.
Dependencies are inferred from the claim text.