Memory testing apparatus and method

A memory testing apparatus for testing a semiconductor memory, comprising:

• a plurality of main cell fail information memories for a main cell array in a semiconductor memory under test, said plurality of fail information memories being provided for a corresponding number of comparator channels, respectively, so that when a comparison result obtained by comparing data read out from said main cell array in said semiconductor memory under test, with an expected value by means of a comparator, indicates a “fail”, fail information is written into the main cell fail information memory at an address corresponding to an address at which said data is read out from said main cell array;
• and
• one redundant cell fail information memory provided for redundant cells in said semiconductor memory under test, one for said plurality of main cell fail information memories, so that a test result of said redundant cells in said semiconductor memory under test is written into said redundant cell fail information memory,
• wherein, when said redundant cells in said semiconductor memory under test are tested, if a redundant cell tested is a “fail”, fail information is written into said redundant cell fail information memory at an address generated on the basis of a reading address supplied to said redundant cells when the “fail” occurs, and respective comparison results outputted in parallel from said comparator channels.

A memory testing method for testing a semiconductor memory having redundant cells in addition to a main cell array, as a device under test, by use of a memory testing apparatus,

• the memory testing apparatus comprising:
• a plurality of main cell fail information memories for said main cell array in the semiconductor memory under test, said plurality of fail information memories being provided for a corresponding number of comparator channels, respectively;
• and
• one redundant cell fail information memory provided for said redundant cells in said semiconductor memory under test, one for said plurality of main cell fail information memories, so that a test result of said redundant cells in said semiconductor memory,
• wherein, when at least one of respective comparison results outputted from a plurality of comparators, each of which compares an output signal outputted from said semiconductor memory under test with an expected value, indicates a “fail”, an address is synthesized from said respective comparison results outputted in parallel from said plurality of comparator and an address supplied to said semiconductor memory under test when the “fail” occurs, and fail information is written into said redundant cell fail information memory at said address thus synthesized, so that fail information represented by a plurality of fail information bits outputted in parallel from said plurality of comparators is written into one cell within said fail information memory with one writing access.