Semiconductor integrated circuit device having a hierarchical power source configuration

A semiconductor integrated circuit device comprising:

• a main voltage transmission line for transmitting a voltage of a first logic level;
• a plurality of sub voltage transmission lines;
• a plurality of resistive elements respectively connected between respective ones of said plurality of sub voltage transmission lines and said main voltage transmission line;
• and
• a plurality of gate circuits respectively divided into groups corresponding to said plurality of sub voltage transmission lines and operating with voltages on their corresponding sub voltage transmission lines as one operating source voltages, each said gate circuit performing a predetermined logic process on a received signal for outputting.

A semiconductor integrated circuit device comprising:

• a first main voltage transmission line for transmitting a voltage of a first logic level;
• a plurality of first sub voltage transmission lines;
• a plurality of first resistive elements connected between respective ones of said plurality of first sub voltage transmission lines and said first main voltage transmission line;
• a second main voltage transmission line for transmitting a voltage of a second logic level;
• a plurality of second sub voltage transmission lines respectively disposed corresponding to said plurality of first sub voltage transmission lines;
• a plurality of second resistive elements connected between respective ones of said plurality of second sub voltage transmission lines and said second main voltage transmission line;
• and
• a plurality of gate circuits divided into a plurality of groups corresponding to respective pairs of said plurality of first sub voltage transmission lines and said plurality of second sub voltage transmission lines, each of the gate circuits operating with both voltages on corresponding first and second sub voltage transmission lines respectively as one operating source voltage and another operating source voltage, each the gate circuit performing a predetermined logic process on a received signal for outputting.

A semiconductor integrated circuit device comprising:

• a main voltage transmission node for supplying a voltage of a first logic level;
• a sub voltage transmission node;
• a voltage supply node for supplying a voltage of a second logic level;
• a logic gate operating with a voltage on said sub voltage transmission node and a voltage on said voltage supply node both as operating source voltages to perform a predetermined logic process on a received signal for outputting;
• and
• a variable resistance element connected between said sub voltage transmission node and said main voltage transmission node and coupled to have a resistance value thereof reduced in response to a signal outputted from said logic gate being at the first logic level.

A semiconductor integrated circuit device comprising:

• a main voltage transmission node for supplying a voltage of a first logic level;
• a sub voltage transmission node;
• a voltage supply node for supplying a voltage of a second logic level;
• a logic gate operating with a voltage on said sub voltage transmission node and a voltage on said voltage supply node both as operating source voltages to perform a predetermined logic process on a received signal for outputting;
• and
• an insulated gate type field effect transistor connected between said main voltage transmission node and said sub voltage transmission node, and having a gate connected to said sub voltage transmission node, said insulated gate type field effect transistor causing a punchthrough phenomenon when the difference between a voltage on said main voltage transmission node and the voltage on said sub voltage transmission node reaches a predetermined value or greater.

A method of manufacturing a semiconductor integrated circuit device, comprising the steps:

• simultaneously forming first and second gate electrode layers on a first conductivity type semiconductor substrate region, said first and second gate electrode layers being separated from each other;
• implanting ions into the substrate region to form impurity regions in self-alignment with the first and second gate electrode layers and forming first and second insulated gate type field effect transistors between which an impurity region formed in the substrate region between the first and second gate electrode layers is shared;
• covering a region for forming the first insulated gate type field effect transistor with a mask layer;
• obliquely implanting ions into a region of the second insulated gate field effect transistor in self-alignment with the second gate electrode layer to reduce a distance between impurity regions of the second insulated gate field effect transistor;
• and
• connecting the first gate type electrode layer and a signal input node with one another, connecting the second gate electrode layer of the second insulated gate type field effect transistor and the impurity region formed between the first and second gate electrode layers with one another and connecting the remaining impurity region of the second insulated gate field effect transistor and a node for supplying a voltage of a first logic level to each other.

A semiconductor integrated circuit device comprising:

• a main voltage transmission line for transmitting a voltage of a first logic level;
• a plurality of sub voltage transmission lines;
• a plurality of gate circuits grouped corresponding to said plurality of sub voltage transmission lines respectively, each the gate circuit performing a predetermined process on a received signal for outputting;
• a plurality of first switching transistors provided corresponding to said plurality of sub voltage transmission lines respectively, each the first switching transistor connecting a corresponding sub voltage transmission line to said main voltage transmission line in response to a group specification signal for specifying a sub voltage transmission line;
• and
• a plurality of second switching transistors provided corresponding to said plurality of sub voltage transmission lines respectively, each the second switching transistor transmitting a voltage closer to a voltage of a second logic level than to the voltage of the first logic level to a corresponding sub voltage transmission line upon non designation by the group specification signal.

A semiconductor integrated circuit device comprising:

• a memory array having a plurality of memory cells arranged in rows and columns;
• a plurality of word lines disposed corresponding to said rows respectively and connected with memory cells on corresponding rows;
• a plurality of decoders each provided corresponding to two word lines, each the decoder decoding a first address signal inputted thereto and outputting a decode signal indicative of the result of decoding therefrom;
• a plurality of first word drivers provided corresponding to said plurality of decoders respectively, each the first word driver transmitting a high voltage to a first word line of corresponding two word lines in accordance with a decode signal outputted from a corresponding decoder and a second address signal;
• a global high voltage supply line for supplying a high voltage greater than an operating source voltage;
• a first sub high voltage transmission line supplied with the high voltage from said global high voltage supply line, for supplying the high voltage to each of said plurality of first word drivers;
• a first switching transistor connected between said global high voltage supply line and said first sub high voltage transmission line to conduct in response to a first control signal;
• a plurality of second word drivers disposed corresponding to said plurality of decoders respectively and arranged in line with corresponding decoders and corresponding first word drivers along a row direction, each the second word driver transmitting the high voltage to a second word line of the corresponding two word lines in response to the signal outputted from the corresponding decoder and a signal complementary to the second address signal;
• a second sub high voltage transmission line supplied with the high voltage from said global high voltage supply line, for supplying the high voltage to said plurality of second word drivers;
• and
• a second switching transistor connected between said global high voltage supply line and said second sub high voltage transmission line to conduct in response to a second control signal.

A semiconductor integrated circuit device comprising:

• a memory array having a plurality of memory cells arranged in rows and columns;
• a plurality of word lines disposed so as to corresponding to the rows respectively and connected with the memory cells on corresponding rows;
• a plurality of decoders disposed corresponding to respective pairs of two word lines, each the decoder decoding a first address signal specifying a word line pair and outputting a decode signal indicative of the result of decoding therefrom;
• a global high voltage supply line for transmitting a high voltage generated from a high voltage generating circuit;
• first and second main high voltage transmission lines coupled to said global high voltage supply line;
• first and second sub high voltage transmission lines each supplied with the high voltage from said global high voltage supply line, said first and second sub high voltage transmission lines transmitting the supplied high voltage and disposed in parallel to and away from said first and second main high voltage transmission lines;
• first and second switching transistors respectively connected between said global high voltage supply line and said first sub high voltage transmission line and between said global high voltage supply line and said second sub high voltage transmission line, for connecting said global high voltage supply line and a corresponding sub high voltage transmission line to each other upon conduction thereof;
• and
• regions for forming first and second word drivers provided corresponding to said plurality of decoders respectively and disposed in line along a row extending direction.

An internal voltage generating circuit comprising:

• a first capacitor having one electrode node supplied with a first clock signal having a predetermined amplitude and another electrode node connected to an internal node;
• an insulated gate field effect transistor having one conduction electrode node connected to the internal node, another conduction electrode node connected to an output node and a gate electrode node;
• a first precharge element for precharging the internal node to a predetermined voltage level corresponding to a first logic level;
• a second precharge element for precharging the gate electrode node of said insulated gate field effect transistor to the predetermined voltage level corresponding to the first logic level;
• a drive element for outputting a signal at a voltage level on the output node in response to a second clock signal different in phase from the first clock signal being at a second logic level;
• and
• a second capacitor having one electrode node connected to an output of said drive element and another electrode node connected to the gate electrode node of said insulated gate field effect transistor;
• said insulated gate field effect transistor being brought into a conductive state when said drive element outputs the signal having the voltage level on the output node.