Semiconductor memory device

Abstract

A semiconductor memory device, that uses redundant memory cell clusters sharing one data transfer bus line to perform defect recovery for a plurality of defects, and provides an improved rate of recovery. The semiconductor memory device is formed from a main memory, a sub-memory functioning as cache memory, and a plurality of data transfer bus lines, which are configured so that data can be transferred bi-directionally between said main memory and said sub-memory; and performs defect recovery for defects located in said main memory based on an address signal (sub-memory column selecting signal SYm) for said sub-memory and address signals (main memory row selecting signal DXn and bank selecting signal BS) in said main memory, which correspond to said address.

Dependencies are inferred from the claim text.