Semiconductor integrated circuit device capable of performing operational test for contained memory core at operating frequency higher than that of memory tester

A semiconductor integrated circuit device, comprising:

• a memory circuit operating in synchronization with an operational clock signal and performing given operational directions;
• and
• a test interface circuit supplying said operational clock signal and said operational directions to said memory circuit and communicating data with said memory circuit according to test directions input in synchronization with a test clock signal during testing,
• said test interface circuit including
• a test clock control terminal receiving a selection signal for selecting a frequency of said operational clock signal in said testing, and
• a frequency multiplication circuit generating, according to said test clock signal, an internal test clock signal to be supplied as said operational clock signal to said memory circuit, and
• said frequency multiplication circuit outputting, according to said selection signal, one of said test clock signal and a clock signal generated by multiplying a frequency of said test clock signal as said internal test clock signal.