Computer system controller having internal memory and external memory control
OwnerNeal Margulisinventor
Life of this patent
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Abstract
The present invention relates generally to an optimized memory architecture for computer systems and, more particularly, to integrated circuits that implement a memory subsystem that is comprised of internal memory and control for external memory. The invention includes one or more shared high-bandwidth memory subsystems, each coupled over a plurality of buses to a display subsystem, a central processing unit (CPU) subsystem, input/output (I/O) buses and other controllers. Additional buffers and multiplexers are used for the subsystems to further optimize system performance.
Claims33
A computer system having a common display memory and main memory, comprising:
- a display means;
- a first plurality of internal and external memory subsystems;
- a second plurality of memory channels;
- a memory channel data switch and controller unit for allocating the memory channels among a plurality of subsystems;
- a central processing unit (CPU) subsystem controller unit producing output signals to be applied to the memory channel data switch and controller unit;
- a graphics/drawing and display subsystem producing output signals to be applied to the memory channel data switch and controller unit;
- an arbitration and control unit producing output signals to be applied to the CPU subsystem controller unit and to the graphics/drawing and display subsystem;
- a peripheral bus control unit producing output signals to be applied to the memory channel data switch and controller unit and to the arbitration and control unit;
- and
- a direct input/output (I/O) control unit producing output signals to be applied to the memory channel data switch and controller unit and to the arbitration and control unit.
A computer system having a common display memory and main memory, comprising:
- a display means;
- a first plurality of internal and external memory subsystems;
- a second plurality of memory channels;
- a memory channel data switch and controller unit for allocating the memory channels among a plurality of subsystems;
- a central processing unit (CPU) subsystem controller unit producing output signals to be applied to the memory channel data switch and controller unit;
- a graphics/drawing and display subsystem producing output signals to be applied to the memory channel data switch and controller unit;
- an arbitration and control unit producing output signals to be applied to the CPU subsystem controller unit and to the graphics/drawing and display subsystem;
- and
- a peripheral bus control unit producing output signals to be applied to the memory channel data switch and controller unit and to the arbitration and control unit.
A computer system having a common display memory and main memory, comprising:
- a display means;
- a plurality of internal and external memory subsystems, each having its own memory channel;
- a memory channel data switch and controller unit wherein the memory channels can be allocated to a plurality of processor or peripheral subsystems;
- a CPU subsystem controller unit producing output signals received proportionally by the memory channel data switch and controller unit;
- and
- an arbitration and control unit producing output signals received proportionally by the CPU subsystem controller unit.
An computer system having a plurality of internal and external memory subsystems comprising:
- multiple concurrent memory channels;
- a memory channel data switch and controller unit wherein the memory channels can be allocated to a plurality of processor or peripheral subsystems;
- a means for a plurality of processors and peripheral subsystems to access the common memory regions;
- and
- at least one of the internal memory subsystems is DRAM memory.
A monolithic integrated circuit comprising:
- at least one internal memory subsystem of DRAM memory;
- at least one external memory control for DRAM memory;
- a plurality of concurrent memory channels;
- and
- a means for multiple compute engines, multiple processors or peripheral subsystems to access the memory channels.
A computer system having a common display memory and main memory, comprising:
- a display means;
- a plurality of internal and external memory subsystems;
- a central processing unit (CPU) subsystem controller unit producing output signals;
- a graphics/drawing and display subsystem producing output signals;
- an arbitration and control unit producing output signals to be applied to the CPU subsystem controller unit and to the graphics/drawing and display subsystem;
- and
- a peripheral bus control unit producing output signals to be applied to the CPU controller unit and to the arbitration and control unit.
Dependencies are inferred from the claim text.