High-resistance load sram

A SRAM comprising a semiconductor substrate, a plurality of memory cells arranged in a matrix on said semiconductor substrate, a pair of bit lines disposed for each column of said memory cells, and a word line disposed for each row of said memory cells,

• each of said memory cells including first and second drive transistors each having a source connected to a ground line, a drain implemented by a first diffused region and a gate, a first transfer transistor having a first source/drain region implemented by said first diffused region of said first drive transistor, a second source/drain region connected to one of said bit lines and a gate connected to corresponding said word line, a second transfer transistor having a first source/drain region implemented by said first diffused region of said second drive transistor, a second source/drain region connected to the other of said bit lines and a gate connected to corresponding said word line, a first resistor implemented by a first contact plug connecting said first diffused region of said first drive transistor and said gate of said second drive transistor with a source line, and a second resistor implemented by a second contact plug connecting said fist diffused region of said second drive transistor and said gate of said first drive transistor with said source line.