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US 2001/0040258 A1Published application
Dual gate dielectric construction
AssigneeMicron Technology, Inc.
InventorsFernando Gonzalez, Roger Lee
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AssigneeMicron Technology, Inc.
InventorsFernando Gonzalez, Roger Lee
Estimating the term…
Dual gate dielectric constructions and methods therefor are disclosed for different regions on an integrated circuit. In the illustrated embodiment, gate dielectrics in memory array regions of the chip are formed of silicon oxide, while the gate dielectric in the peripheral region comprises a harder material, specifically silicon nitride, and has a lesser overall equivalent oxide thickness. The illustrated peripheral gate dielectric has an oxide-nitride-oxide construction. The disclosed process includes forming silicon nitride over the entire chip followed by selectively etching off the silicon nitride from the memory array region, without requiring a separate mask as compared to conventional processes. After the selective etch, oxide is grown over the entire chip, growing differentially thicker in the memory array region.
An integrated circuit, comprising:
A system comprising a semiconductor substrate having a plurality of first transistors and second transistors, each of the first transistors including a first gate insulator comprising silicon nitride, and each of the second transistors including a second gate insulator consisting essentially of silicon oxide.
An integrated memory chip, comprising logic circuits and memory array circuits formed on a semiconductor substrate, the logic circuits comprising a plurality of transistor gate dielectrics of a first construction including a layer of a first material, the memory array circuits comprising a plurality of transistor gate dielectrics of a second construction consisting essentially of a second material, wherein the dielectric constant of the first material is different from the dielectric constant of the second material.
A memory chip having at least one memory array and a logic circuit, the memory array comprising a plurality of array gate electrodes separated from a semiconductor substrate by a gate oxide, the logic circuit comprising a plurality of logic circuit gate electrodes separated from the substrate by a gate dielectric comprising silicon nitride and silicon oxide, wherein the gate oxide has an equivalent oxide thickness greater than an equivalent oxide thickness of the gate dielectric.
Dependencies are inferred from the claim text.