Programmable logic controller method, system and apparatus
AssigneeSiemens Aktiengesellschaft
InventorsMark Steven Boggs, Temple L. Fulton, Steve Hausman, Gary McNabb, Alan McNutt, Steven W. Stimmel
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AssigneeSiemens Aktiengesellschaft
InventorsMark Steven Boggs, Temple L. Fulton, Steve Hausman, Gary McNabb, Alan McNutt, Steven W. Stimmel
Estimating the term…
A programmable logic controller with enhanced and extended the capabilities. A digital input filter implement filters with considerable less logic by simulating the action of a capacitor being driven by a constant current source whose output voltage is sensed by a comparator with a large amount of hysteresis. A pulse catch circuit captures the input pulse even though the update occurs between scan cycles. A pulse output controller includes a hardware pipeline mechanism to allow for smooth, hardware-controlled transitions from wave-form to wave-form. A free port link allows the user to control the port either manually or by operation of a user program. In order to provide higher performance for communication using PPI protocol, the PLC includes a built-in protocol. An n-bit modem protocol ensures data integrity without use of a parity type data integrity system. A hide instruction protects proprietary software by encrypting the sensitive code and decrypting the code during compilation and, thereafter, re-encrypting the code. A system function call allows the user to create and/or download new PLC functions and implement them as PLC operating system functions. An STL status function debugs programs during run-time and while the program is executing. A micro PLC arrangement provides compact size and efficiency.
A pipeline apparatus for use in a pulse output block that provides smooth, controlled transitions from wave-form to wave-form, wherein said pulse output block operates on the basis of a cycle time, a delta cycle time and a pulse count/width value, said apparatus comprising:
A method for providing smooth, controlled transitions from wave-form to wave-form in a pulse output block that operates on the basis of a cycle time, a delta cycle time and a pulse count/width value, said method comprising the steps of:
An apparatus that provides a free port mode that allows a user to control a free port that links to a programmable logic controller, said apparatus comprising:
A method for providing a free port mode that allows a user to control a free port that links to a programmable logic controller, said method comprising the steps of:
An apparatus for an n-bit protocol, n being an integer, for a modem wherein said n-bit protocol eliminates a parity bit of an n+1 bit protocol that includes said parity bit employed for parity checking an integrity of data transmitted in said n+1 bit protocol, said n-bit protocol comprising:
A method for generating an n-bit protocol, n being an integer, for a modem wherein said n-bit protocol eliminates a parity bit of an n+1 bit protocol that includes said parity bit employed for parity checking an integrity of data transmitted in said n+1 bit protocol, said n-bit protocol comprising:
A method for debugging a program in real time and while said program is executed by a programmable logic controller, said method comprising the steps of:
An apparatus that debugs a program in real time and while said program is executed by a programmable logic controller, said method comprising the steps of:
An apparatus for high speed discrete output, said apparatus comprising:
A method for high speed discrete output, said method comprising the steps of:
An apparatus for supporting customized function calls in a programmable logic controller having a predetermined set of function calls, said apparatus comprising:
A method for supporting customized function calls in a programmable logic controller having a predetermined set of function calls, said method comprising the steps of:
Dependencies are inferred from the claim text.