Methods and apparatuses for signal processing

A method of performing saturated multiplication and accumulation on a non-vectorized equation, the method comprising:

• multiplying a plurality of digital samples with a plurality of coefficients to generate a plurality of terms;
• adding a first term formed by the multiplying to an accumulated value to determine if the positive saturation value or the negative saturation value are met or exceeded as indicated by the carry output from the addition in order to limit the addition thereto or select the added value as a first add output;
• adding a second term formed by the multiplying to the first add output to determine if the positive saturation value or the negative saturation value are met or exceeded as indicated by the carry output from the addition in order to limit the addition thereto or select a plurality of added results as a second add output;
• adding a third term formed by the multiplying to the second add output to determine if the positive saturation value or the negative saturation value are met or exceeded as indicated by the carry output from the addition in order to limit the addition thereto or select a plurality of added results as a third add output;
• adding a fourth term formed by the multiplying to the first add output to determine if the positive saturation value or the negative saturation value are met or exceeded as indicated by the carry output from the addition in order to limit the addition thereto or provide a plurality of added results as a fourth add output;
• and
• selecting either the negative saturation value, the positive saturation value, or one of the plurality of added results of the fourth add output as the result of the non-vectorized equation, whereby the terms of the non-vectorized equation are formed in one clock cycle by simultaneous multiplication and addition.

A gateway interface of a gateway for connecting multiple networks and devices that may use different communication protocols, the gateway interface for packetizing information from the multiple devices for communication over a packetized network, the gateway interface including:

• network interface devices coupled to a receive bus and a transmit bus, the network interface devices to couple to the multiple networks and devices that may use different communication protocols to receive information and couple it to the receive bus and to couple to the transmit bus to receive information on the transmit bus and couple to the packetized network to transmit information in a packetized form,
• at least one application specific signal processing unit coupled to a local memory, the receive bus, and the transmit bus, the at least one application specific signal processing unit to perform saturated multiplication and accumulation of the information received, the at least one application specific signal processing unit including
• a serial interface to receive data samples of a digital signal and transmitting a digital signal processed output;
• a buffer memory to couple to the serial interface, the buffer memory to buffer the received data samples of the digital signal prior to digital signal processing and to buffer the digital signal processed output prior to transmission;
• at least one core processor to digital signal process the digital signal, the at least one core processor to generate the digital signal processed output in response to the data samples of the digital signal and a digital signal processing algorithm and to couple to the buffer memory to buffer the digital signal processed output prior to transmission, the at least one core processor including,
• a reduced instruction set computer (RISC) processor to provide control of the generation of the digital signal processed output, and
• a plurality of signal processing units executing the digital signal processing algorithm and processing the digital samples in parallel, the plurality of signal processing units generating the digital signal processed output in response to the data samples of the digital signal and the digital signal processing algorithm.

A gateway interface for performing saturated multiplication and accumulation, the gateway interface having a processor, the gateway interface comprising:

• a processor readable storage medium;
• and
• code recorded in the processor readable storage medium
• to multiply a plurality of digital samples with a plurality of coefficients to generate a plurality of terms;
• to add a first term formed by the multiplication to an accumulated value to determine if a positive saturation value or a negative saturation value are met or exceeded as indicated by the carry output of the addition in order to limit the addition thereto or select the added value as a first add output;
• to add a second term formed by the multiplication to the first add output to determine if the positive saturation value or the negative saturation value are met or exceeded as indicated by the carry output of the addition in order to limit the addition thereto or select a plurality of added results as a second add output;
• to add a third term formed by the multiplication to the second add output to determine if the positive saturation value or the negative saturation value are met or exceeded as indicated by the carry output from the addition in order to limit the addition thereto or select a plurality of added results as a third add output;
• to add a fourth term formed by the multiplication to the first add output to determine if the positive saturation value or the negative saturation value are met or exceeded as indicated by the carry output from the addition in order to limit the addition thereto or provide a plurality of added results as a fourth add output and
• to select either the negative saturation value, the positive saturation value, or one of the plurality of added results of the fourth add output as the result of the non-vectorized equation, whereby the terms of the non-vectorized equation are evaluated by performing multiplication and addition in one step.