US 2001/0037435 A1 · Distributed address mapping and routing table mechanism that supports flexible configuration and partitioning in a modular switch-based, shared-memory multiprocessor computer system

Abstract

A distributed address mapping and routing technique supports flexible configuration and partitioning in a modular, shared memory multiprocessor system having a plurality of multiprocessor building blocks interconnected by a switch fabric. The technique generally employs physical-to-logical address translation mapping in conjunction with source routing. Mapping operations, such as address range or processor identifier operations, used to determine a routing path through the switch fabric for a message issued by a source multiprocessor building block are resolved through the generation of a routing word. That is, each message transmitted by a source multiprocessor building block over the switch fabric has an appended routing word that specifies the routing path of the message through the fabric.

Claims28

Dependent claims

A method for implementing hard partitions and high availability in a modular, shared memory multiprocessor system defining an address space and having a plurality of multiprocessor nodes interconnected by a switch fabric, the nodes configured to generate and exchange messages, the method comprising the steps of:

providing each processor of a node with a processor identifier (ID);
partitioning the multiprocessor system into a plurality of hard partitions, each hard partition including at least one multiprocessor node;
mapping the system address space so as to provide a physical address of zero within each hard partition;
mapping the processor IDs so as to provide a single processor with a processor ID of zero within each hard partition;
and
blocking messages originating in a first hard partition from entering a second hard partition.

3 more elements

A modular, shared memory multiprocessor system comprising:

a switch fabric;
a plurality of multiprocessor building blocks interconnected by the switch fabric and configured to generate and send messages across the switch fabric, one or more of the multiprocessor building blocks including a memory system having a starting memory address;
and
mapping logic disposed at each multiprocessor building block, wherein
at least some of the messages carry an address of a destination multiprocessor building block, and
the mapping logic is configured to (1) generate a routing word for the messages in response to a translation mapping operation performed on the destination address of the message, the routing word specifying a routing path of the message through the switch fabric, and (2) append the routing the word to the message.

3 more elements

Dependencies are inferred from the claim text.

Distributed address mapping and routing table mechanism that supports flexible configuration and partitioning in a modular switch-based, shared-memory multiprocessor computer system

Life of this patent

Distributed address mapping and routing table mechanism that supports flexible configuration and partitioning in a modular switch-based, shared-memory multiprocessor computer system

Life of this patent

Abstract

Claims28