Information processing apparatus with parallel accumulation capability

An information processing apparatus comprising:

• a memory for storing data;
• a first memory controller for outputting a read address and controlling reading of the data stored in said memory;
• a first initial address register for storing an initial value of the read address output from said first memory controller;
• a first register controlled by said first memory controller to store the data read from said memory;
• an accumulator for accumulating the data stored in said first register;
• a second register for storing a result of accumulation by said accumulator;
• an initialize for initializing said accumulator and outputting the result of accumulation stored in said second register to said memory;
• a second memory controller for outputting a write address and writing the result of accumulation stored in said second register to said memory;
• a second initial address register for storing an initial value of the write address output from said second memory controller;
• an accumulator count register for storing a frequency of repetition of accumulation and an accumulated data count indicating a number of data items to be accumulated by said accumulator and;
• and
• a controller for timing initialization of said accumulator by said initialize, based on the accumulated data count stored in said accumulator count register, for controlling timing of output of the initial read address from said first memory controller, based on the accumulated data count and the frequency of repetition of accumulation stored in said accumulator count register, and for controlling timing of output of the initial write address from said second memory controller, based on the accumulated data count and the frequency of repetition of accumulation stored in said accumulator count register, wherein
• reading, by said first memory controller, of the data from said memory into said first register, accumulation of the read data in said accumulator, and writing, by said second memory controller, of the result of accumulation to said memory proceed in parallel in each cycle of accumulation.