Interrupt handling via a proxy processor

Abstract

A translation technique facilitates servicing of device interrupts by a proxy processor of a multiprocessor system having an interrupt delivery/handling subsystem. A target processor of the system is originally designated to service the interrupts, whereas the proxy processor is configured to service the interrupts in response to hot-swap of the target processor. The translation technique provides dual mapping of a device interrupt queue (DIQ) associated with the target processor and used to store vectors describing the device interrupts. The dual mapping technique allows the DIQ to be accessed via either a “fast access” or “slow access” mode. The fast access mode provides optimized access to the DIQ by the target processor via processor-specific space addressing, whereas the slow access mode provides slower, yet flexible, access to the DIQ by any other processor, such as the proxy processor, via general system space addressing.

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