Interrupt processing method in an operation processing device and the device using the same
AssigneeOMRON Corporation
InventorsHiroyuki Yanagi, Yosuke Baba, Yasuhiro Nishimura, Motoyuki Kato, Shiji Nakagawa
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AssigneeOMRON Corporation
InventorsHiroyuki Yanagi, Yosuke Baba, Yasuhiro Nishimura, Motoyuki Kato, Shiji Nakagawa
Estimating the term…
The objective of this invention is to eliminate wasteful use of the memory resource, reduce complexity of program switching or thread interrupt program processing, and speed up program processing. In operation processing devices based on Java (a registered trademark), each time a functional program is executed a memory work area is dynamically created. This invention eliminates the need to maintain a separate memory thread work area for interrupt program processing. It simplifies the processing involved in sidetracking and restoring data required to switch between threads or programs to be executed. The work area for a program being run is a dynamically created memory area according to this invention. When an interrupt is generated, the register data indicating the status and register state of the program being run at that time is sidetracked into the work area for that program. A work area for the interrupt program's processing is created in the aforesaid memory or thread work area and the address needed to return to the work area for the program being run when the aforesaid interrupt was generated is sidetracked in this work area. When the interrupt program's processing is completed, register state data is returned from the aforesaid sidetracked address to the work area for the program being run when the aforesaid interrupt was generated. Using the register data sidetracked in that work area, the processor restores the status and register state of the program being run at the time the aforesaid interrupt was generated.
An interrupt processing method to temporally interrupt a executing main program used in an operation processing device by setting a work area dynamically in a memory, comprising a step of:
An operation processing device provided with an interruption function, comprising:
Dependencies are inferred from the claim text.