US 2001/0037424 A1 · Snoop phase in a highly pipelined bus architecture

Abstract

A bus agent that may be used in an enhanced highly pipelined bus architecture. In one embodiment, the bus agent includes a set of snoop status interfaces, an address strobe signal interface, and a bus clock interface for a bus clock signal. The bus agent of this embodiment also includes bus controller logic capable of sensing or asserting one or more of a set of snoop status signals for transaction N on the snoop status interfaces during a snoop phase to start in a bus cycle upon the later of three or more bus clock cycles of the bus clock signal after a beginning of a bus cycle of an the assertion of an address strobe signal for transaction N or two or more bus clock cycles of the bus clock signal after a beginning of a bus cycle in which a most recent snoop phase begins.

Claims22

Dependent claims

A bus agent comprising:

a plurality of snoop status interfaces;
an address strobe signal interface;
a bus clock interface for a bus clock signal;
bus controller logic capable of sensing or asserting one or more of a plurality of snoop status signals for transaction N on said plurality of snoop status interfaces during a snoop phase to start in a bus cycle upon a later one of:
three or more bus clock cycles of the bus clock signal after a beginning of a bus cycle of an assertion of an address strobe signal for transaction N;
or
two or more bus clock cycles of the bus clock signal after a beginning of a bus cycle in which a most recent snoop phase begins.

4 more elements

A system comprising:

a first bus agent comprising:
a plurality of snoop status interfaces;
an address strobe interface;
a bus clock interface for a bus clock signal;
bus controller logic to start a transaction N by asserting an address strobe on the address strobe interface, said first bus controller being capable of sensing one or more of a plurality of snoop status signals for the transaction N on said plurality of snoop status interfaces during a snoop phase occurring upon a later one of:
three or more bus clock cycles of the bus clock signal after a beginning of a bus clock cycle of an assertion of an address strobe for transaction N;
or
a most recent snoop phase for another transaction has been observed completed for zero or more clocks;
a second bus agent coupled to the first bus agent, said second bus agent comprising:
a second plurality of snoop status interfaces;
a second address strobe interface;
a second bus clock interface for a bus clock signal;
a second bus controller logic to receive the address strobe on the second address strobe interface, said second bus controller being capable of asserting one or more of said plurality of snoop status signals for the transaction N on said plurality of snoop status interfaces during a snoop phase occurring upon a later one of:
three or more bus clock cycles of the bus clock signal after the beginning of the bus clock cycle of the assertion of the address strobe for transaction N;
or
the most recent snoop phase for another transaction has been observed completed for zero or more clocks.

13 more elements

Dependencies are inferred from the claim text.

Snoop phase in a highly pipelined bus architecture

Life of this patent

Snoop phase in a highly pipelined bus architecture

Life of this patent

Abstract

Claims22