Logic circuits and carry-lookahead circuits

A logic circuit comprising:

• a dynamic logic circuit composed of a first combinational logic circuit connected between an output line and a ground level, said output line of said dynamic logic circuit being pulled up to a “H” level during the precharge period, while said output line is disconnected from said ground level and an electric power source is supplied to said output line, by controlling input signals to the first combinational logic circuit;
• said first combinational logic circuit being given input signals to be evaluated during an evaluation period while said output line is disconnected from said electric power source so that said dynamic logic circuit serves to output a logic value corresponding to an logic operation by the use of the input signals;
• a pseudo-NMOS circuit composed of a second combinational logic circuit connected between an output line and a ground level, said output line of said pseudo-NMOS circuit being pulled down to a “L” level during the precharge period, while said output line is connected to said ground level, by controlling input signals to the first combinational logic circuit;
• said second combinational logic circuit being given input signals to be evaluated while an electric power source is supplied to said output line during an evaluation period so that said pseudo-NMOS circuit serves to output a logic value corresponding to an logic operation by the use of the input signals by selectively disconnecting said output line from said ground level;
• and
• a logic gate connected to said dynamic logic circuit and serving to control the supply of the electric power source to said output line of said pseudo-NMOS circuit in accordance with the signal of said output line of said dynamic logic circuit,
• wherein said dynamic logic circuit and said pseudo-NMOS circuit are complementary and wherein said logic gate serves to cut off the supply of the electric power source to said output line of said pseudo-NMOS circuit, when said output line of said pseudo-NMOS circuit and said ground level are connected during the evaluation period to pull down said output line to the “L” level, in response to the corresponding change of said output line of said dynamic logic circuit.

Pseudo-NMOS logic circuit comprising:

• a first pseudo-NMOS circuit composed of a first combinational logic circuit connected between an output line and a ground level, said output line of said pseudo-NMOS circuit being pulled down to a “L” level during the precharge period, while said output line is connected to said ground level, by controlling input signals to the first combinational logic circuit;
• said first combinational logic circuit being given input signals to be evaluated while an electric power source is supplied to said output line during an evaluation period so that said first pseudo-NMOS circuit serves to output a logic value corresponding to an logic operation by the use of the input signals by selectively disconnecting said output line from said ground level;
• and
• a second pseudo-NMOS circuit composed of a second combinational logic circuit connected between an output line and a ground level, said output line of said pseudo-NMOS circuit being pulled down to a “L” level during the precharge period, while said output line is connected to said ground level, by controlling input signals to the second combinational logic circuit;
• said second combinational logic circuit being given input signals to be evaluated while an electric power source is supplied to said output line during an evaluation period so that said second pseudo-NMOS circuit serves to output a logic value corresponding to an logic operation by the use of the input signals by selectively disconnecting said output line from said ground level;
• and
• a first logic gate connected to said second pseudo-NMOS circuit and serving to control the supply of the electric power source to said output line of said first pseudo-NMOS circuit in accordance with the signal of said output line of said second pseudo-NMOS logic circuit,
• a second logic gate connected to said first pseudo-NMOS circuit and serving to control the supply of the electric power source to said output line of said second pseudo-NMOS circuit in accordance with the signal of said output line of said first pseudo-NMOS logic circuit,
• wherein said first pseudo-NMOS logic circuit and said second pseudo-NMOS logic circuit are complementary and wherein one of said first logic gate and said second logic gate serves to cut of f the supply of the electric power source to said output line of one of said first pseudo-NMOS circuit and said second pseudo-NMOS circuit during the evaluation period in response to the corresponding change of said output line of the other of said first pseudo-NMOS circuit and said second pseudo-NMOS circuit to a “H” level.

A carry lookahead circuit for generating a group propagate signal PG and at least one of a group generate signal GG and a group kill signal KG for a group of m bits (m is an integer no less than 1) by the use of propagate signals P, generate signals G and kill signals K respectively for the constituent bits of the group, said carry lookahead circuit comprising:

• a logic circuit for outputting a logic value as said group propagate signal PG and/or the inversion of said logic value as the inversion of said group propagate signal PGB when all of said propagate signals P take said logic value or when all of the inversion of the propagate signals PB take the inversion of said logic value;
• a priority encoder for searching said propagate signals P and/or the inversion of said propagate signals PB from the most significant bit to the least significant bit for detecting the inversion of said logic value in said propagate signals P and/or for detecting said logic value in the inversion of said propagate signals PB in order to generate selection signals of m bits one of which is activated corresponding to said propagate signal P detected to take the inversion of said logic value and/or corresponding to the inversion of said propagate signal PB detected to take said logic value
• said priority encoder serving to generate said selection signals of which no bit is activated in order to indicate that there is no bit to be selected, when the inversion of said logic value is not detected in said propagate signals P or when said logic value is not detected in the inversion of said propagate signals PB;
• and
• a selector circuit for receiving said selection signals S, selecting one of the generate signals G and/or one of the kill signals K corresponding to the activated bit of said selection signals and outputting said one of the generate signals G and/or said one of the kill signals K as selected as said group generate signal GG and/or said group kill signal KG when there is a bit to be selected of said selection signals,
• said selector circuit serving to output the inversion of said logic value as said group generate signal GG and/or said group kill signal KG when there is no bit to be selected of said selection signals.

A carry lookahead circuit for generating a group propagate signal PG, a group carry signal CG and at least one of a group generate signal GG and a group kill signal KG for a group of m bits (m is an integer no less than 1) by the use of a carry signal C, propagate signals P, generate signals G and kill signals K respectively for the constituent bits of the group, said carry lookahead circuit comprising:

• a logic circuit for outputting a logic value as said group propagate signal PG and/or the inversion of said logic value as the inversion of said group propagate signal PGB when all of said propagate signals P take said logic value or when all of the inversion of the propagate signals PB take the inversion of said logic value;
• a priority encoder for searching said propagate signals P and/or the inversion of said propagate signals PB from the most significant bit to the least significant bit for detecting the inversion of said logic value in said propagate signals P and/or for detecting said logic value in the inversion of said propagate signals PB in order to generate selection signals of m bits one of which is activated corresponding to said propagate signal P detected to take the inversion of said logic value and/or corresponding to the inversion of said propagate signal PB detected to take said logic value
• said priority encoder serving to generate said selection signals of which no bit is activated in order to indicate that there is no bit to be selected, when the inversion of said logic value is not detected in said propagate signals P or when said logic value is not detected in the inversion of said propagate signals PB;
• and
• a selector circuit for receiving said selection signals S, selecting one of the generate signals G and one of the kill signals K corresponding to the activated bit of said selection signals and outputting said one of the generate signals G and said one of the kill signals K as selected as said group carry signal CG and the inversion of said carry signal CGB when there is a bit to be selected of said selection signals,
• said selector circuit serving to output said carry signal C as said group carry signal CG responsive to said group propagate signal PG and the inversion of group propagate signal PGB.

A carry lookahead circuit comprising:

• a plurality of first carry lookahead circuit groups each of which is composed of a plurality of first carry lookahead circuits;
• a second carry lookahead circuit group which is composed of a plurality of second carry lookahead circuits each of which is connected to those of said first carry lookahead circuits belonging to respective one of said first carry lookahead circuit groups;
• and
• a third carry lookahead circuit connected to said second carry lookahead circuits,
• wherein each of said first carry lookahead circuits is a carry lookahead circuit for generating a first group propagate signal and at least one of a first group generate signal and a first group kill signal for a group of m bits (m is an integer no less than 1) by the use of propagate signals, generate signals and kill signals respectively for the constituent bits of the group, each of said first carry lookahead circuits comprising:
• a logic circuit for outputting a logic value as said first group propagate signal and/or the inversion of said logic value as the inversion of said first group propagate signal when all of said propagate signals take said logic value or when all of the inversion of the propagate signals take the inversion of said logic value;
• a priority encoder for searching said propagate signals and/or the inversion of said propagate signals from the most significant bit to the least significant bit for detecting the inversion of said logic value in said propagate signals and/or for detecting said logic value in the inversion of said propagate signals in order to generate selection signals of m bits one of which is activated corresponding to said propagate signal detected to take the inversion of said logic value and/or corresponding to the inversion of said propagate signal detected to take said logic value
• said priority encoder serving to generate said selection signals of which no bit is activated in order to indicate that there is no bit to be selected, when the inversion of said logic value is not detected in said propagate signals or when said logic value is not detected in the inversion of said propagate signals;
• and
• a selector circuit for receiving said selection signals S, selecting one of the generate signals and/or one of the kill signals corresponding to the activated bit of said selection signals and outputting said one of the generate signals and/or said one of the kill signals as selected as said first group generate signal and/or said first group kill signal when there is a bit to be selected of said selection signals,
• said selector circuit serving to output the inversion of said logic value as said first group generate signal and/or said first group kill signal when there is no bit to be selected of said selection signals,
• wherein each of said second carry lookahead circuits is a carry lookahead circuit for generating a second group propagate signal and at least one of a second group generate signal and a second group kill signal for a corresponding first carry lookahead circuit group by the use of said first group propagate signals, said first group generate signals and said first group kill signals respectively output from the constituent carry lookahead circuits of said corresponding first carry lookahead circuit group, each of said second carry lookahead circuits comprising:
• a logic circuit for outputting said logic value as said second group propagate signal and/or the inversion of said logic value as the inversion of said second group propagate signal when all of said first group propagate signals take said logic value or when all of the inversion of the first group propagate signals take the inversion of said logic value;
• a priority encoder for searching said first group propagate signals and/or the inversion of said first group propagate signals from the most significant bit to the least significant bit for detecting the inversion of said logic value in said first group propagate signals and/or for detecting said logic value in the inversion of said first group propagate signals in order to generate selection signals of a plurality of bits one of which is activated corresponding to said first group propagate signal detected to take the inversion of said logic value and/or corresponding to the inversion of said first group propagate signal detected to take said logic value
• said priority encoder serving to generate said selection signals of which no bit is activated in order to indicate that there is no bit to be selected, when the inversion of said logic value is not detected in said first group propagate signals or when said logic value is not detected in the inversion of said first group propagate signals;
• and
• a selector circuit for receiving said selection signals S, selecting one of the first group generate signals and/or one of the first group kill signals corresponding to the activated bit of said selection signals and outputting said one of the first group generate signals and/or said one of the first group kill signals as selected as said second group generate signal and/or said second group kill signal when there is a bit to be selected of said selection signals,
• said selector circuit serving to output the inversion of said logic value as said second group generate signal and/or said second group kill signal when there is no bit to be selected of said selection signals.
• wherein each of said third carry lookahead circuits is a carry lookahead circuit for generating a third group propagate signal, a group carry signal and at least one of a third group generate signal and a third group kill signal for a corresponding first carry lookahead circuit group by the use of a carry signal, said second group propagate signals, said second group generate signals and said second group kill signals respectively output from the constituent carry lookahead circuits of said corresponding second carry lookahead circuit group, each of said third carry lookahead circuits comprising:
• a logic circuit for outputting a logic value as said third group propagate signal and/or the inversion of said logic value as the inversion of said third group propagate signal when all of said second group propagate signals take said logic value or when all of the inversion of the second group propagate signals take the inversion of said logic value;
• a priority encoder for searching said second group propagate signals and/or the inversion of said second group propagate signals from the most significant bit to the least significant bit for detecting the inversion of said logic value in said second group propagate signals and/or for detecting said logic value in the inversion of said second group propagate signals in order to generate selection signals of a plurality of bits one of which is activated corresponding to said second group propagate signal detected to take the inversion of said logic value and/or corresponding to the inversion of said second group propagate signal detected to take said logic value
• said priority encoder serving to generate said selection signals of which no bit is activated in order to indicate that there is no bit to be selected, when the inversion of said logic value is not detected in said second group propagate signals or when said logic value is not detected in the inversion of said second group propagate signals;
• and
• a selector circuit for receiving said selection signals S, selecting one of the second group generate signals and one of the second group kill signals corresponding to the activated bit of said selection signals and outputting said one of the second group generate signals and said one of the second group kill signals as selected as said group carry signal and the inversion of said carry signal when there is a bit to be selected of said selection signals,
• said selector circuit serving to output said carry signal as said group carry signal responsive to said third group propagate signal and the inversion of said third group propagate signal.