Method of formation of conductive lines on integrated circuits
AssigneeSTMicroelectronics S.r.l.
InventorYvon Gris
Life of this patent
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Abstract
The present invention relates to a method of formation of a conductive line on integrated circuits including the steps of etching a first insulator layer to create therein openings of predetermined width at the locations where the conductive line is to be formed; depositing and etching a first interconnection layer of a first thickness; and depositing and etching a second interconnection layer of a second thickness; the predetermined width being higher than twice the greatest of the two thicknesses, and lower than twice the sum of the thicknesses.
Claims7
A method of formation of a conductive line on integrated circuits including the steps of:
- etching a first insulator layer to create therein openings of predetermined width at locations where the conductive line is to be formed,
- depositing and etching a first interconnection layer of a first thickness, and
- depositing and etching a second interconnection layer of a second thickness,
- wherein the predetermined width is greater than twice the greatest of the two thicknesses, and smaller than twice the sum of the thicknesses.
A conductive line formed on a surface of a substrate, the upper surface of the substrate comprising an insulating layer in which is formed an opening of predetermined width at the location where the conductive line is to be formed, including a first interconnection layer of a first thickness and a second interconnection layer of a second thickness, the predetermined width being greater than twice the greatest of the two thicknesses, and smaller than twice the sum of the thicknesses.
Dependencies are inferred from the claim text.