Conductive lines, coaxial lines, integrated circuitry, and methods of forming conductive lines, coaxial lines, and integrated circuitry

A method of forming a co-axial line comprising:

• forming a masking material layer over a substrate;
• patterning the masking material layer to form at least one conductive line pattern;
• forming an inner conductive layer within the at least one conductive line pattern;
• vapor depositing a layer comprising a polymer dielectric material over at least some of the inner conductive layer;
• and
• forming an outer conductive layer over the polymer dielectric material.

A method of forming a co-axial line comprising:

• forming a pair of upstanding, spaced-apart conductive terminal members over a substrate;
• forming a co-axial inner conductive line component which extends between and electrically connects with the terminal members;
• surrounding a substantial portion of the inner conductive line component with a dielectric polymer layer;
• and
• forming a co-axial outer conductive line component over the dielectric polymer layer.

A method of forming a co-axial line comprising:

• forming a pair of upstanding, spaced-apart terminal members over a substrate;
• forming photoresist over the terminal members;
• forming a line pattern within the photoresist which exposes and extends between the terminal members;
• sputtering a first conductive layer of material over the co-axial line pattern;
• electroplating a second conductive material over the first conductive layer;
• forming a dielectric layer over the second conductive material surrounding a substantial portion thereof;
• and
• forming an outer conductive sheath of material over the dielectric layer.

A method of forming a co-axial line comprising:

• forming a pair of upstanding, spaced-apart terminal members over a substrate;
• forming photoresist over the terminal members;
• forming a line pattern within the photoresist which exposes and extends between the terminal members;
• electroless plating a conductive material over the co-axial line pattern;
• forming a dielectric layer over the conductive material;
• and
• forming an outer conductive sheath of material over the dielectric layer.

A method of forming a co-axial line comprising:

• providing a substrate having an outer surface;
• forming a pair of upstanding, spaced-apart conductive terminal members over the substrate outer surface;
• forming a layer of photoresist over the substrate outer surface;
• forming a conductive line pattern in the photoresist, the conductive line pattern extending at least between and exposing portions of the conductive terminal members;
• forming a layer of conductive material over the substrate and within the conductive line pattern;
• removing a sufficient amount of material of the layer of conductive material to electrically isolate the conductive material within the conductive line pattern;
• removing photoresist from at least around a conductive material portion which extends between the spaced-apart conductive terminal members, the removing of the photoresist leaving the conductive material portion supported above underlying substrate outer surface;
• vapor depositing a polymer dielectric material comprising Parylene, the depositing of the Parylene completely surrounding the conductive material portion which extends between the spaced-apart conductive terminal members;
• and
• vapor depositing a conductive material at least over the Parylene which surrounds the conductive material portion which extends between the spaced-apart conductive terminal members.

Integrated circuitry comprising:

• a semiconductive substrate having an outer surface;
• an inner conductive core spaced from and over the outer surface;
• a polymer dielectric layer surrounding a substantial portion of the inner conductive core;
• and
• an outer conductive sheath surrounding a substantial portion of the polymer dielectric layer.

Integrated circuitry comprising:

• a semiconductive substrate having an outer surface;
• a pair of spaced-apart terminal members disposed over the outer surface and extending elevationally away therefrom;
• an inner conductive core operably connected with and extending between the spaced-apart terminal members;
• a polymer dielectric layer over a substantial portion of the inner conductive core;
• and
• an outer conductive sheath surrounding a substantial portion of the polymer dielectric layer.

Integrated circuitry comprising:

• a substrate having an outer surface;
• a pair of upstanding, spaced-apart conductive terminal members disposed over the substrate outer surface;
• a copper-comprising layer of material operably connected with and extending between the terminal members, the copper-comprising layer having a thickness of between about 100 to 200 nanometers;
• a conductive layer of material disposed over and operably connected with the copper-comprising layer of material, the conductive layer comprising conductive material selected from the group consisting of copper, gold, nickel, cobalt, and iron;
• a dielectric layer comprising Parylene disposed over the conductive layer of material, the dielectric layer surrounding conductive layer portions which extend between the terminal members;
• and
• an outer conductive sheath of material disposed over the dielectric layer and surrounding dielectric layer portions which extend between the terminal members.