Active load address buffer

A method of replicating cached data in a redundantly threaded processor, wherein the method comprises:

• executing a load instruction associated with a leading thread to retrieve a data value from a data cache;
• determining if a pending invalidate bit associated with an address of said data value is set;
• if the pending invalidate bit is not set:
• incrementing a counter associated with said address of said data value;
• executing a load instruction associated with a trailing thread to retrieve said data value from the data cache;
• and
• decrementing said counter.

A computer system, comprising:

• a simultaneously and redundantly threaded (“SRT”) processor;
• an I/O controller coupled to said processor;
• an I/O device coupled to said I/O controller;
• and
• an main system memory coupled to said processor;
• wherein said SRT processor processes a set of program instructions as a leading thread and also as a trailing thread, wherein at least on of the program instructions is a load instruction that causes the processor to retrieve a data value from a data cache, and wherein the processor includes:
• an active load address buffer having entries that include an address field and a counter field, wherein when the processor processes the load instruction in the leading thread, the address field is set to indicate an address of the data value and the counter field is incremented, and wherein when the processor processes the load instruction in the trailing thread, the address field is searched to locate the entry whose address field is set to indicate the address of the data value, and the counter field is decremented.