Multi-bit scoreboarding to handle write-after-write hazards and eliminate bypass comparators

Abstract

What is disclosed is an apparatus including a set of data storage units having a set of scoreboard bits associated with the set of data storage units; a first execution unit having an output coupled to the data storage unit and a first input; a first switching unit having an output coupled to the first input of the first execution unit and a first input coupled to the output of the first execution unit; and, a first bypass control unit coupled to the first switching unit; wherein the first bypass control unit is configured to cause the first switching unit to couple the output of the first switching unit to the first input of the first switching unit based upon the set of scoreboard bits. What is also disclosed is a method including the steps of receiving a first instruction; and, storing a first address location and a first access path specifier for a first operand associated with the first instruction; wherein the first access path specifier indicates a source of the first operand. The method and apparatus allows the elimination of bypass comparators and also handles write-after-write hazards.

Dependencies are inferred from the claim text.