Method of fabricating a DRAM cell configuration
AssigneeInfineon Technologies AG
InventorBernd Gobel
Life of this patent
Estimating the term…
Abstract
A depression is produced in a substrate for a capacitor of a memory cell of the DRAM cell configuration. An insulation and a storage node of the capacitor are produced in the depression. A spacer made of silicon is produced above the storage node. A first part of the spacer is doped by inclined implantation. The spacer is patterned by utilizing the different doping of the first part of the spacer. With the aid of the patterned spacer as a mask, the storage node and the insulation are altered in such a way that the storage node directly adjoins the substrate only in a limited patch of a sidewall of the depression and is otherwise isolated from the substrate by the insulation.
Claims11
A method of fabricating a DRAM cell configuration, which comprises the following steps:
- producing a depression with sidewalls in a substrate;
- producing in the depression an insulation and a storage node of a capacitor, wherein the capacitor is at least partly isolated from the substrate by the insulation;
- by deposition, etching back, and inclined implantation of silicon, producing a spacer of silicon above the storage node in the depression along sidewalls of the depression, wherein a first part of the spacer and a second part, opposite the first part, of the spacer are doped differently;
- patterning the spacer by removing one of the first part of the spacer and the second part of the spacer utilizing the different doping thereof;
- altering the insulation and a first part of the storage node disposed under the removed part of the spacer, such that either the first part of the storage node or a second part of the storage node disposed under the remaining part of the spacer, adjoins the substrate, and thereby utilizing the patterned spacer as a mask;
- producing a transistor of the memory cell such that a first source/drain region is formed in the substrate adjoining the storage node;
- producing and connecting a word line to a gate electrode of the transistor;
- and
- producing a bit line running transversely with respect to the word line and connecting the bit line to the memory cell.
The method according to claim 17 which comprises
- first producing the storage node and the insulation such that both the first part of the storage node and the second part of the storage node adjoin the substrate;
- removing the first part of the storage node and thereby using the patterned spacer as a mask;
- and
- enlarging the insulation such that the insulation replaces the first part of the storage node.
Dependencies are inferred from the claim text.