US 2001/0033615 A1 · Automatic equalization circuit and receiver circuit using the same

Abstract

A digital multilevel signal receiver circuit which can sufficiently improve transmission efficiency while suppressing a data transmission error, and an automatic equalization circuit for use in the digital multilevel signal receiver circuit. An equalization training automatic equalizer is provided separately from a data reproducing equalizer having equalization characteristics which can be set up. A received training signal is once stored in a memory, read out from the memory and supplied to the equalization training automatic equalizer so as to update tap coefficients of the equalizer. The updated tap coefficients are given to the data reproducing equalizer so as to update equalization characteristics of the equalizer. A received data signal is equalized with the updated equalization characteristics.

Claims14

Dependent claims

An automatic equalization circuit for receiving a digital training signal and a digital data signal and outputting a digital data signal equalized, comprising:

a first automatic equalization unit, to which said digital training signal and a digital data signal are supplied, for equalizing said digital data signal;
a memory for storing said digital training signal;
and
a second automatic equalization unit coupled with said memory, for outputting an updating signal therefrom, the equalization characteristic of which is updated on the basis of said digital training signal from said memory, wherein said updating signal from said second automatic equalization unit is supplied to said first automatic equalization unit, so that the equalization characteristic of said first automatic equalization unit is updated.

1 more element

Dependencies are inferred from the claim text.

Automatic equalization circuit and receiver circuit using the same

Life of this patent

Automatic equalization circuit and receiver circuit using the same

Life of this patent

Abstract

Claims14