Multi-protocol packet translator
OwnerPaul C. Dorsey, Kevin M. Frazier +1inventors
InventorsPaul C. Dorsey, Kevin M. Frazier, Peter DeCarolis
Life of this patent
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Abstract
A multi-protocol packet translator is disclosed. The translator may have microcoded control to translate a packet from one protocol to another. The microcoded instructions may be fed through a pipeline to control reading of information from information sources (including the original packet) and selectively connecting those sources to an output memory.
Claims21
A translator unit for translating a packet formatted according to a first protocol into a packet according to a second protocol, the translator unit comprising:
- an input memory;
- at least one information source;
- an output memory;
- a connection circuit, coupled to the input memory, the information source and the output memory, to selectively connect the input memory and the information source to the output memory;
- and
- a microcoded control unit coupled to the connection circuit.
A pipelined control unit for reading data, comprising:
- a first memory having a first read latency;
- a second memory having a second read latency, longer than the first read latency;
- a pipeline unit having a first stage and a second stage;
- a circuit, coupled to the pipeline unit, the first memory and the second memory, to initiate read cycles from the first memory based on a first instruction in the second stage of the pipeline, and to initiate read cycles from the second memory based on a second instruction in the first stage of the pipeline.
A method of translating an original packet from a first protocol to a second protocol, comprising steps of:
- loading a first memory with a plurality of sets of microcode instructions, each set being designed to perform a different network communication protocol translation;
- receiving the original packet;
- selecting a one of the sets of microcode instructions, based on the identity of the first protocol and the identity of the second protocol;
- and
- translating the original packet into a translated packet by executing the selected set of microcode instructions.
A method of translating an original packet into a translated packet, comprising steps of:
- loading an instruction memory with a set of instructions;
- loading the original packet into an input memory, the input memory having a first read latency;
- providing an information source;
- providing an output memory to store the translated packet;
- sequentially, selectively connecting the input memory and the information source to the output memory, based on the instructions.
Dependencies are inferred from the claim text.