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US 2001/0033522 A1Published application
Semiconductor memory
AssigneeKabushiki Kaisha Toshiba
InventorHaruki Toda
Life of this patent
Estimating the term…
Abstract
Banks are arranged on a memory chip, forming a matrix. A data input/output circuit is provided at one side of the memory chip. A data bus is provided among the banks and connected to the data input/output circuit. Each bank has a plurality of memory cell arrays a cell-array controller, a row decoder, column decoders, and a DQ buffer. The cell-array controller and the row decoder oppose each other. The column decoders oppose the DQ buffer. Local DQ lines are provided between the memory cell arrays, and global DQ liens extend over the memory cell arrays. The local DQ lines extend at right angles to the global DQ lines.
Claims84
A semiconductor memory according comprising:
- A. a memory chip;
- B. a plurality of banks arranged on said memory chip, for storing and outputting multi-bit data, independently of one another, each comprising:
- a. a plurality of memory-cell blocks, each comprising two sub-blocks, sense amplifiers, word lines, data lines and column-selecting lines, each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells;
- b. at least one column decoder located at at least a first end of every column of memory cells and connected to said column-selecting lines;
- c. a plurality of row decoders located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block;
- d. a plurality of DQ buffers located at a second end of every row of memory cells, each of said DQ buffers provided for one memory-cell block;
- e. a cell-array controller located at a second end of very row of memory cells, for controlling the reading and writing of the multi-bit data;
- C. a data input/output region provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device;
- and
- D. a data bus provided for said plurality of banks, extending parallel to the columns of memory cells, for transferring multi-bit data between said plurality of banks, one the one hand, and said data input/output region, on the other.
7 more elements
A semiconductor memory according comprising:
- A. a memory chip;
- B. a plurality of main banks arranged on said memory chip, for storing and outputting multi-bit data, independently of one another, each composed of a plurality of sub-banks, each of which comprises:
- a. a plurality of memory-cell blocks, each comprising two sub-blocks, sense amplifiers, word lines, data lines and column-selecting lines, each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells;
- b. at least one column decoder located at at least a first end of every column of memory cells and connected to said column-selecting lines;
- c. a plurality of row decoders located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block;
- d. a plurality of DQ buffers located at a second end of every row of memory cells, each of said DQ buffers provided for one memory-cell block;
- e. a cell-array controller located at a second end of very row of memory cells, for controlling the reading and writing of the multi-bit data;
- C. a data input/output region provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device;
- and
- D. a plurality of data buses provided for at least two of said sub-banks, extending parallel to the columns of memory cells, for transferring multi-bit data between said sub-banks, one the one hand, and said data input/output region, on the other.
7 more elements
A semiconductor memory according comprising:
- A. a memory chip;
- B. a plurality of banks arranged on said memory chip, for storing and outputting multi-bit data, independently of one another, each comprising:
- a. a plurality of memory-cell blocks, each comprising two sub-blocks, sense amplifiers, word lines, data lines and column-selecting lines, each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells;
- b. at least one column decoder located at a first end of every column of memory cells and connected to said column-selecting lines;
- c. a plurality of row decoders located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block;
- d. a plurality of DQ buffers located at a second end of every row of memory cells;
- e. a cell-array controller located at the first end of very row of memory cells, for controlling the reading and writing of the multi-bit data;
- C. a data input/output region provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device;
- and
- D. a data bus provided for said plurality of banks, extending parallel to the columns of memory cells, for transferring multi-bit data between said plurality of banks, one the one hand, and said data input/output region, on the other.
7 more elements
A semiconductor memory according comprising:
- A. a memory chip;
- B. a plurality of main banks arranged on said memory chip, for storing and outputting multi-bit data, independently of one another, each composed of a plurality of sub-banks, each of which comprises:
- a. a plurality of memory-cell blocks, each comprising two sub-blocks, sense amplifiers, word lines, data lines and column-selecting lines, each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells;
- b. at least one column decoder located at a first end of every column of memory cells and connected to said column-selecting lines;
- c. a plurality of row decoders located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block;
- d. a plurality of DQ buffers located at a second end of every column of memory cells;
- e. a cell-array controller located at the first end of very row of memory cells, for controlling the reading and writing of the multi-bit data;
- C. a data input/output region provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device;
- and
- D. a plurality of data buses provided for at least two of said sub-banks, extending parallel to the rows of memory cells, for transferring multi-bit data between said sub-banks, one the one hand, and said data input/output region, on the other.
7 more elements
A semiconductor memory according comprising:
- A. a memory chip;
- B. a plurality of main banks arranged on said memory chip, for storing and outputting multi-bit data, independently of one another, each composed of a plurality of sub-banks, each of which comprises:
- a. a plurality of memory-cell blocks, each comprising two sub-blocks, sense amplifiers, word lines, data lines and column-selecting lines, each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells;
- b. at least one column decoder located at a first end of every column of memory cells and connected to said column-selecting lines;
- c. a plurality of row decoders located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block;
- d. a plurality of DQ buffers located at a second end of every row of memory cells, each of said DQ buffers provided for one memory-cell block;
- e. a cell-array controller located at the first end of very row of memory cells, for controlling the reading and writing of the multi-bit data;
- C. a plurality of data input/output regions provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device;
- and
- D. a plurality of data buses provided for at least two of said sub-banks, extending parallel to the rows of memory cells, for transferring multi-bit data between said sub-banks, one the one hand, and said data input/output regions, on the other,
- wherein said input/output regions are spaced apart along the rows of memory cells, said data buses are arranged on both sides of each of said data input/output regions and spaced apart along the columns of memory cells, and said sub-banks are arranged on both sides of each of said data buses.
8 more elements
A test circuit for testing a semiconductor memory comprising a memory cell array composed of a plurality of memory-cell blocks, data-writing means for writing bits of data simultaneously into memory cells of at least one of the memory-cell blocks, and a register for holding the data to be written into said at least one of the memory-cell blocks, said test circuit comprising:
- write/read means for writing the data held in said register into the memory cells of said at least one of the memory-cell blocks and for reading data from said memory cells;
- comparing means for comparing the data held in said register with the data read from said memory cells to determine whether the semiconductor memory is flawless and for generating data representing whether the semiconductor memory is flawless;
- and
- an output circuit for outputting the data generated by said comparing means, from the semiconductor memory.
1 more element
A test circuit for testing a semiconductor memory comprising a memory cell array composed of a plurality of memory-cell blocks, data-writing means for writing n-bit data simultaneously into memory cells of n memory cell-blocks among said memory-cell blocks, and a register for holding the n-bit data to be written into the n memory cell blocks, said semiconductor memory comprising:
- write/read means for writing the data held in said register into the memory cells of said n memory-cell blocks and for reading data from said memory cells;
- comparing means for comparing the n-bit data held in said register with the n-bit data read from said memory cells to determine whether the semiconductor memory is flawless and for generating n-bit data representing whether the semiconductor memory is flawless;
- and
- an output circuit for outputting the n-bit data generated by said comparing means, from the semiconductor memory.
1 more element
A data transfer system comprising:
- a plurality of switch blocks arranged in a line parallel to column of switches, each comprising:
- a switch array each having a plurality of switches arranged in the form of a matrix;
- a row decoder provided at one of two sides of said switch array which extend at right angles to row of switches;
- a local DQ line provided to one side of switch array and extending parallel to the rows of switches;
- and
- a data line connected to switches of said switch array, for supplying data to said local DQ line;
- a global DQ line extending over said switch blocks, in parallel to the column of switches, and connected at one end to said local DQ line;
- a column decoder provided at one side of said switch blocks, for selecting column of switches provided in said switch blocks;
- and
- a data input/output circuit provided at one side of said switch blocks and connected to the other end of said global DQ line, for receiving and outputting data.
7 more elements
A memory system according comprising:
- A. a memory chip;
- B. a plurality of banks arranged on said memory chip, for storing and outputting multi-bit data in synchronism with a clock signal, independently of one another, each comprising:
- a. a plurality of memory-cell blocks;
- each comprising two sub-blocks, sense amplifiers, word lines, data lines and column-selecting lines, each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells;
- b. at least one column decoder located at at least a first end of every column of memory cells and connected to said column-selecting lines;
- c. a plurality of row decoders located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block;
- d. a plurality of DQ buffers located at a second end of every row of memory cells, each of said DQ buffers provided for one memory-cell block;
- e. a cell-array controller located at a second end of very row of memory cells, for controlling the reading and writing of the multi-bit data;
- C. a data input/output region provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device;
- D. a data bus provided for said plurality of banks, extending parallel to the columns of memory cells, for transferring multi-bit data between said plurality of banks, one the one hand, and said data input/output region, on the other;
- E. a CPU chip generating said clock signal;
- and
- F. an I/O bus connecting between said memory chip and said CPU chip.
10 more elements
A memory system according comprising:
- A. a memory chip;
- B. a plurality of main banks arranged on said memory chip, for storing and outputting multi-bit data in synchronism with a clock signal, independently of one another, each composed of a plurality of sub-banks, each of which comprises:
- a. a plurality of memory-cell blocks, each comprising two sub-blocks, sense amplifiers, word lines, data lines and column-selecting lines, each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells;
- b. at least one column decoder located at at least a first end of every column of memory cells and connected to said column-selecting lines;
- c. a plurality of row decoders located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block;
- d. a plurality of DQ buffers located at a second end of every row of memory cells, each of said DQ buffers provided for one memory-cell block;
- e. a cell-array controller located at a second end of very row of memory cells, for controlling the reading and writing of the multi-bit data;
- C. a data input/output region provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device;
- D. a plurality of data buses provided for at least two of said sub-banks, extending parallel to the columns of memory cells, for transferring multi-bit data between said sub-banks, one the one hand, and said data input/output region, on the other;
- E. a CPU chip generating said clock signal;
- and
- F. an I/O bus connecting between said memory chip and said CPU chip.
9 more elements
A memory system according comprising:
- A. a memory chip;
- B. a plurality of banks arranged on said memory chip, for storing and outputting multi-bit data in synchronism with a clock signal, independently of one another, each comprising:
- a. a plurality of memory-cell blocks, each comprising two sub-blocks, sense amplifiers, word lines, data lines and column-selecting lines, each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells;
- b. at least one column decoder located at a first end of every column of memory cells and connected to said column-selecting lines;
- c. a plurality of row decoders located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block;
- d. a plurality of DQ buffers located at a second end of every row of memory cells;
- e. a cell-array controller located at the first end of very row of memory cells, for controlling the reading and writing of the multi-bit data;
- C. a data input/output region provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device;
- D. a data bus provided for said plurality of banks, extending parallel to the columns of memory cells, for transferring multi-bit data between said plurality of banks, one the one hand, and said data input/output region, on the other;
- E. a CPU chip generating said clock signal;
- and
- F. an I/O bus connecting between said memory chip and said CPU chip.
9 more elements
A memory system according comprising:
- A. a memory chip;
- B. a plurality of main banks arranged on said memory chip, for storing and outputting multi-bit data in synchronism with a clock signal, independently of one another, each composed of a plurality of sub-banks, each of which comprises:
- a. a plurality of memory-cell blocks, each comprising two sub-blocks, sense amplifiers, word lines, data lines and column-selecting lines, each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells;
- b. at least one column decoder located at a first end of every column of memory cells and connected to said column-selecting lines;
- c. a plurality of row decoders located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block;
- d. a plurality of DQ buffers located at a second end of every column of memory cells;
- e. a cell-array controller located at the first end of very row of memory cells, for controlling the reading and writing of the multi-bit data;
- C. a data input/output region provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device;
- D. a plurality of data buses provided for at least two of said sub-banks, extending parallel to the rows of memory cells, for transferring multi-bit data between said sub-banks, one the one hand, and said data input/output region, on the other;
- E. a CPU chip generating said clock signal;
- and
- F. an I/O bus connecting between said memory chip and said CPU chip.
9 more elements
A memory system according comprising:
- A. a memory chip;
- B. a plurality of main banks arranged on said memory chip, for storing and outputting multi-bit data in synchronism with a clock signal, independently of one another, each composed of a plurality of sub-banks, each of which comprises:
- a. a plurality of memory-cell blocks, each comprising two sub-blocks, sense amplifiers, word lines, data lines and column-selecting lines, each of said sub-blocks composed of one memory cell array, said sense amplifiers located between said two sub-blocks, said word lines, data lines and column-selecting lines arranged on the memory cell arrays constituting said two sub-blocks, said memory-cell blocks spaced apart along columns of memory cells and the column-selecting lines and data lines, and said sub-blocks spaced apart also along the columns of memory cells;
- b. at least one column decoder located at a first end of every column of memory cells and connected to said column-selecting lines;
- c. a plurality of row decoders located at a first end of every row of memory cells along which said word line extend, and connected to said word lines, each of said row decoders provided for one memory-cell block;
- d. a plurality of DQ buffers located at a second end of every row of memory cells, each of said DQ buffers provided for one memory-cell block;
- e. a cell-array controller located at the first end of very row of memory cells, for controlling the reading and writing of the multi-bit data;
- C. a plurality of data input/output regions provided on said memory chip, for receiving multi-bit data from an external device and outputting multi-bit data to an external device;
- D. a plurality of data buses provided for at least two of said sub-banks, extending parallel to the rows of memory cells, for transferring multi-bit data between said sub-banks, one the one hand, and said data input/output regions, on the other,
- wherein said input/output regions are spaced apart along the rows of memory cells, said data buses are arranged on both sides of each of said data input/output regions and spaced apart along the columns of memory cells, and said sub-banks are arranged on both sides of each of said data buses;
- and
- E. a CPU chip generating said clock signal;
- and
- F. an I/O bus connecting between said memory chip and said CPU chip.
11 more elements
Dependencies are inferred from the claim text.