Semiconductor memory device

Abstract

The semiconductor memory device according to the present invention comprises a memory cell array having a plurality of bit lines, a plurality of word lines installed perpendicular to the plurality of bit lines, and a plurality of memory cells disposed at the intersections of the bit lines and the word lines, a row decoder which selects a prescribed word line out of the plurality of word lines in response to a row address when a control signal is in an activated state and brings all the word lines to an unselected state when the control signal is changed to an inactivated state, a test mode decision circuit which generates a test signal by deciding that the device is in a test mode, and a control signal generating circuit which brings the control signal to the activated state and keeps it there for a prescribed duration in response to an instruction signal, wherein the control signal generating circuit has a means for setting the change of the control signal to the inactivated state in response to the occurrence of the test signal sooner than in a normal operation.

Dependencies are inferred from the claim text.