Interleaved memory device for burst type access in synchronous read mode with the two semi-arrays independently readable in random access asynchronous mode

An interleaved memory readable in sequential access synchronous mode and in random access asynchronous mode, having two banks of memory cells (EVEN_MATRIX, ODD_MATRIX) each provided with an internal address counter (EVEN_COUNTER, ODD_COUNTER, ODD_REGISTER), decoding structures (X-DEC-EVEN, X-DEC-ODD, Y-DEC-EVEN, Y-DEC-ODD) and reading circuitry (SA, SA_LATCHES, SA_OUT_BUS), input address buffers (ADD BUFFERS), control signal buffers (CEn BUFFER, OEn BUFFER, ALE CON) and output data buffers (BUFFOUT), a control circuit (TIMING) receiving external commands of enabling of the memory (CEn), of enabling of the input address buffers (ALE), of stimulation of reading (RD) and of enabling of the output buffers (OEn) and at least an input address buffers transition detecting signal (ATD) generated by a dedicated generator circuit (ATD GEN), characterized in that

• said generator (ATD GEN) generates a transition detecting signal (ATD) upon a change of the address acquired from outside in said address buffers (ADD BUFFERS) during a random access phase and upon the generation of an increment pulse (INC_E, INC_O) of one or the other of said internal address counters of said two banks in a sequential access phase;
• said decoding and reading structures of the two banks are functionally independent from each other, each including a dummy wordline (EV_WL_OK, OD_WL_OK) and a dummy sense amplifier EV SA-DUMMY, OD SA-DUMMY) controlling the equalization phase of the sense amplifiers of the respective array (EVEN_SIDE SAs, ODD_SIDE SAs) of the bank and a logic circuit (EV SENSE-CON, OD SENSE-CON) enabling the sensing, terminating the sensing and latching phase of the read datum in the respective buffers (SA_LATCHES) in cascade to the output of said sense amplifiers;
• an internal data bus for the transfer of data stored in said latches (SA_LATCHES) of the respective array of sense amplifiers of one or the other bank (EVEN_SIDE, SAs, SA_LATCHES, ODD_SIDE SAs, SA_LATCHES) to an array of output buffers (BUFFOUT) under control of a load signal (LOAD_E, LOAD_O) specific for one and the other bank generated by said control circuit (TIMING);
• the control circuit (TIMING) discriminating the access and reading mode requested from a specific protocol of use of said external commands of enabling of the input address buffers (ALE) and of reading stimulation (RD);
• a transition to a high logic state of said first external signal (ALE 0→1), enabling the acquisition of an input address and the start of a new random access asynchronous read cycle with a simultaneous activation of the sense amplifier arrays and of respective reading circuitry of both banks (EVEN_SIDE SAs, ODD_SIDE SAs);
• permanence of said external signal (ALE) to a high logic state (ALE=1) maintaining the memory in a random access asynchronous read mode, said second external signal (RD) acting as active low clock of the transfer of the data read from the bank currently in priority, established by the value of the least significant bit of the externally acquired address, in the respective output latches of the reading circuitry of the bank;
• return of said first external signal (ALE) to a low logic state (ALE→0) causing the switching to a sequential (burst) access synchronous read mode by generating within said control circuit a first increment pulse (INC_E, INC_O) for the counter of internal addresses of the bank currently not in priority, implementing an outphasing between the two banks from the first synchronous mode read cycle and the generation of a transition detecting signal (ATD) for the bank not in priority, a sequential and interleaved reading of data stored in said two banks progressing under control of said second external signal of reading stimulation (RD) and of said load signal (LOAD_E, LOAD_O) of data in the output buffers (BUFFOUT).