Alignment mark configuration
AssigneeTaiwan Semiconductor Manufacturing Company, Ltd.
InventorsLiang-Gi Yao, Jaw-Jung Shin
Life of this patent
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Abstract
An alignment mark configuration, wherein the alignment mark is protected from being damaged from the subsequent planarization process, is described. The alignment mark configuration comprises a plurality of recesses and a flat spacing between the recesses on the substrate. If the substrate further comprises a trench structure, the spacing between the trench structure and the alignment mark is at least 5 times the flat spacing between the neighboring recesses of the alignment mark.
Claims3
An alignment mark configuration, which is applicable on a substrate comprising a plurality of layers, the alignment mark configuration comprising:
- an alignment mark on the substrate, wherein the alignment mark comprises a plurality of recesses and a spacing between the neighboring recesses is “d”;
- and
- a trench, wherein a spacing between the trench and the alignment mark is in a range between about 5d to 80d.
Dependencies are inferred from the claim text.