Lead-less semiconductor device with improved electrode pattern structure

A semiconductor device comprising:

• an insulating substrate have a first main face which is sealed with a sealing material;
• at least a set of input and output electrode patterns provided on said first main face, and said input and output electrode patterns being separated from each other;
• at least a ground electrode pattern having a ground potential, and said ground electrode pattern being provided on an inter-region between said input and output electrode patterns and separated from said input and output electrode patterns;
• and
• a semiconductor chip mounted on said ground electrode pattern.

An electrode pattern structure on a first main face of an insulating substrate, said structure comprising:

• at least a set of input and output electrode patterns being separated from each other;
• at least a ground electrode pattern having a ground potential and being separated from said input and output electrode patterns;
• and
• at least an electrically conductive pattern extending over an inter-region between said input and output electrode patters, and said electrically conductive pattern being separated from said input and output electrode patterns, and said electrically conductive pattern being electrically connected to said ground electrode pattern, so that said electrically conductive pattern has a ground potential.