Interchangeable FPGA-Gate array

Abstract

A test facilitating circuit is contained in a FPGA-GATE ARRAY. In the gate array chip there are disposed I/O cells, a boundary scan circuit, a controller and an internal circuit. The arrangement of the external terminals of a package is the same as the arrangement of the external terminals of the FPGA. The test terminal corresponds to the data program terminal of the FPGA. When the FPGA is displaced with a gate array, the data program terminal of the FPGA becomes unnecessary and is used as a control terminal for the boundary scan circuit. The position of the test terminal is fixed, thereby to achieve a facilitated, automated and standardized design.

Dependencies are inferred from the claim text.