US 2001/0027546 A1 · Semiconductor integrated circuit

Abstract

A logic in DRAM LSI is disclosed, which comprises a plurality of DRAM circuits, a control circuit that receives a test control signal to perform a test control in which the plurality of RAM circuits are tested while the access to the plurality of DRAM circuits is subsequently changed for each row, an input selector that is controlled by the control circuit and inputs a DRAM macro signal to the plurality of DRAM circuits at the time of a test, and an output selector that is controlled by the control circuit, and outputs output signals of the plurality of DRAM circuits sequentially to a macro output terminal at the time of the test. According to the DRAM integrated LSI, a test time required to test the plurality of DRAM circuits integrated in the LSI is shortened. Moreover, data that is read from the plurality of DRAM circuits is transferred in a high speed.

Claims19

Dependent claims

A semiconductor integrated circuit comprising:

a plurality of DRAM circuits;
a control circuit that receives a test control signal to perform a test control in which said plurality of RAM circuits are tested while the access to said plurality of DRAM circuits is subsequently changed for each row;
an input selector that is controlled by said control circuit and inputs a DRAM macro signal to said plurality of DRAM circuits at the time of a test;
and
an output selector that is controlled by said control circuit, and outputs output signals of said plurality of DRAM circuits sequentially to a macro output terminal at the time of the test.

2 more elements

Dependencies are inferred from the claim text.

Facts

Application

09/821,163Filed 28 Mar 2001

Priority

JP 2000-08840828 Mar 2000

Published

4 Oct 2001

Term ends

Not estimatedThe source records don’t support an estimate.

Classification9 codes

G11C 7/1057
Data output circuits, e.g. read-out amplifiers, data output buffers, data output registers, data output level conversion circuits: data output…
G11C 7/1012
Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor: data reordering during…
G11C 7/1051
Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers: data output circuits, e.g. read-out amplifiers,…
G11C 29/14
Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details: implementation of control logic, e.g. test mode…

Semiconductor integrated circuit

Life of this patent

Semiconductor integrated circuit

Life of this patent

Abstract

Claims19