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US 2001/0027006 A1Published application
Semiconductor device and method for fabricating the same
AssigneeHyundai Electronics Industries Co., Ltd.
InventorJae Kap Kim
Life of this patent
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Abstract
A semiconductor device comprising a dual polysilicon gate structure in which the P type polysilicon gate is connected with the N type polysilicon gate by a bilayer conductive wiring structure without any contact, thereby significantly contributing to high integration, and a method for fabricating the semiconductor device such that the production yield is improved.
Claims12
A method for forming conductive wirings in a semiconductor device, comprising the steps of:
- forming a first conductive layer on an insulating layer;
- forming an etch barrier layer on the first conductive layer;
- selectively etching the etch barrier layer by use of a first conductive wiring mask, to form an etch barrier layer pattern;
- forming a second blanket conductive layer over the resulting structure;
- forming a photosensitive film pattern by use of a second conductive wiring mask with an arrangement to overlap with said etch barrier pattern;
- etching the second conductive layer by use of a second conductive wiring mask, to form a second conductive wiring;
- etching the first conductive layer by use of a combination of the photosensitive film pattern and the etch barrier layer pattern as an etch mask, to form a first conductive wiring;
- and
- removing the photosensitive film pattern, to obtain a bilayer conductive wiring structure in which the second conductive wiring stacks up on a part of the first conductive wiring.
6 more elements
A method for fabricating a semiconductor device having a dual polysilicon gate structure, comprising the steps of:
- forming a P well and an N well in a semiconductor substrate and forming an element isolating film on a predetermined area including the boundary of the P well and the N well;
- forming a gate oxide film, a first conductive layer and an etch barrier layer, in sequence;
- etching the etch barrier layer by use of a gate electrode mask consisting of two separate regions, to form an etch barrier layer pattern consisting of two separate regions;
- depositing a blanket second conductive layer and etching it by use of a second conductive wiring mask, to form a second conductive layer pattern, said second conductive wiring mask being arranged so as to overlap both the two separate regions of the etch barrier layer pattern;
- etching the first conductive layer by use of a combination of the second conductive wiring mask and the etch barrier layer as an etch mask, to form a first conductive layer pattern;
- implanting P type impurities into the N well and one part of the first conductive layer pattern by use of a P type ion-implanting mask, to form a P type source/drain electrode and a P type gate electrode, said P type ion-implanting mask being arranged to mask the P well region including the other part of the first conductive layer pattern;
- and
- implanting N type impurities into the P well and the other part of the first conductive layer pattern by use of an N type ion-implanting mask, to form an N type source/drain electrode and an N type gate electrode, said N type ion-implanting mask being arranged to mask the N well region including the one part of the first conductive layer pattern.
5 more elements
A method for fabricating a semiconductor device having a dual polysilicon gate structure, comprising the steps of:
- forming a P well and an N well in a semiconductor substrate and forming an element isolating film on a predetermined area including the boundary of the P well and the N well;
- forming a gate oxide film, a first conductive layer and an oxidation barrier layer, in sequence;
- etching a part of the oxidation barrier layer by use of an N type ion-implanting mask and implanting P type impurities into the N well and one part of the first conductive layer pattern under the P type ion-implanting mask, to form a P type source/drain electrode and a P type gate electrode, said P type ion-implanting mask being arranged to mask the P well region including the other part of the first conductive layer pattern;
- etching another part of the oxidation barrier layer by use of a P type ion-implanting mask, to form an oxidation barrier layer pattern and implanting N type impurities into the P well and another part of the first conductive layer pattern under the N type ion-implanting mask, to form an N type source/drain electrode and an N type gate electrode, said N type ion-implanting mask being arranged to mask the N well region including the one part of the first conductive layer pattern and to overlap with the N type ion-implanting mask;
- thermally growing an oxide into a predetermined thickness on the P type and N type gate electrodes and an exposed surface of the gate oxide film;
- removing the oxidation barrier layer pattern, to expose a part of the gate electrode;
- selectively forming a second conductive layer on the exposed part of the gate electrode, so as to interconnect the N type gate electrode and the P type gate electrode.
4 more elements
A semiconductor device, comprising:
- a P well and an adjacent N well in a semiconductor substrate;
- an element isolating film formed on a predetermined area including the boundary between the P well and the N well;
- gate oxide layers formed on the P well and the N well;
- a dual polysilicon gate structure extending from a part of the P well through the element isolating film to a part of the N well, said dual polysilicon gate consisting of a P type gate electrode and an N type gate electrode, which are on the P well region and the N well region, respectively;
- and
- a conductive layer formed on the dual polysilicon gate structure and for interconnecting the P type gate electrode and the N type gate electrode.
3 more elements
A semiconductor device in accordance with claim 13, wherein said conductive layer is formed of selective tungsten or Ti silicide.
Dependencies are inferred from the claim text.