Power semiconductor element capabale of improving short circuit withstand capability while maintaining low on-voltage and method of fabricating the same

A semiconductor element, comprising:

• a first base layer of a first conductivity type;
• a second base layer of a second conductivity type formed selectively in one surface region of said first base layer;
• an emitter layer or a source layer of the first conductivity type formed selectively in a surface region of said second base layer;
• a gate electrode formed on that portion of said second base layer which is positioned between said emitter layer or source layer and said first base layer with a gate insulating film interposed between said gate electrode and said second base layer;
• a collector layer or a drain layer formed on the other surface region of said first base layer or formed selectively on one surface region of the first base layer;
• a first main electrode formed on said collector layer or on said drain layer;
• a second main electrode formed on said emitter layer or source layer and on said second base layer;
• and
• a third base layer formed within said second base layer so as to be isolated from said emitter layer or source layer and formed in contact with said gate insulating film, the point of the highest impurity concentration of a first impurity concentration profile along the gate insulating film within said third base layer and in the direction in which said emitter layer or source layer, the second base layer, and the first base layer are arranged in the order mentioned being positioned closer to the first base layer than the point of the highest impurity concentration of a second impurity concentration profile along the gate insulating film within said second base layer and in the direction in which the emitter layer or source layer, the second base layer and the first base layer are arranged in the order mentioned.

A semiconductor element, comprising:

• a first base layer of a first conductivity type;
• a second base layer of a second conductivity type formed selectively in one surface region of said first base layer;
• an emitter layer or a source layer of the first conductivity type formed selectively in a surface region of said second base layer;
• a gate electrode formed on that portion of said second base layer which is positioned between said emitter layer or source layer and said first base layer with a gate insulating film interposed between said gate electrode and said second base layer;
• a collector layer or a drain layer formed on the other surface region of said first base layer or formed selectively on one surface region of the first base layer;
• a first main electrode formed on said collector layer or on said drain layer;
• a second main electrode formed on said emitter layer or source layer and on said second base layer;
• and
• a channel region formed in contact with said gate insulating film to permit the carrier to migrate between said emitter layer or source layer and said first base layer, said channel region having an impurity concentration profile such that the impurity concentration is substantially constant along said gate insulating film and in the direction in which the emitter layer or source layer, the second base layer, and the first base layer are formed in the order mentioned.

A method of fabricating a semiconductor element, comprising the steps of:

• selectively forming a second base layer of a second conductivity type in one surface region of a first base layer of a first conductivity type, said second base layer having an impurity concentration profile such that the point of the highest impurity concentration is positioned in a region close to the junction between the second base layer and the first base layer;
• selectively forming an emitter layer or source layer of the first conductivity type in a surface region of said second base layer;
• forming a gate electrode on the surface of that region of said second base layer which is positioned between said emitter layer or source layer and said first base layer with a gate insulating film interposed between said gate electrode and said second base layer;
• selectively forming a collector layer or drain layer in the other surface region of said first base layer or in one surface region of said first base layer;
• and
• forming a first main electrode in contact with said collector layer or drain layer and a second main electrode in contact with said emitter layer or source layer and said second base layer.

A method of fabricating a semiconductor element, comprising the steps of:

• selectively forming a second base layer of a second conductivity type in one surface region of a first base layer of a first conductivity type;
• selectively forming an emitter layer or source layer of the first conductivity type in a surface region of said second base layer;
• forming a gate electrode on the surface of that region of said second base layer which is positioned between said emitter layer or source layer and said first base layer with a gate insulating film interposed between said gate electrode and said second base layer, and a third base layer of the second conductivity type, which is isolated from said emitter layer or source layer, within said second base layer;
• selectively forming a collector layer or drain layer in the other surface region of said first base layer or in one surface region of said first base layer;
• and
• forming a first main electrode in contact with said collector layer or drain layer and a second main electrode in contact with said emitter layer or source layer and said second base layer.

A method of fabricating a semiconductor element, comprising the steps of:

• selectively forming an emitter layer or source layer of a first conductivity type in one surface region of a first base layer of the first conductivity type;
• forming a trench extending through said emitter layer or source layer and having the bottom portion positioned within said first base layer;
• forming a gate insulating film to cover the bottom and the side surface of said trench;
• forming a gate electrode on said gate insulating film;
• forming a groove having a bottom positioned within said first base layer;
• forming a second base layer of the second conductivity type in a surface region of said first base layer such that said second base layer is in contact with said gate insulating film by introducing an impurity of the second conductivity type into said first base layer in the bottom and in the vicinity of the side wall of said groove, followed by applying a thermal diffusion to the introduced impurity;
• forming a third base layer of the second conductivity type within said second base layer such that said third base layer is in contact with said gate insulating film by introducing an impurity of the second conductivity type into the second base layer in the vicinity of the bottom of said groove, followed by applying a thermal diffusion to the introduced impurity;
• selectively forming a collector layer or drain layer in the other surface region of said first base layer;
• and
• forming a first main electrode in contact with said collector layer or drain layer and a second main electrode in contact with said emitter layer or source layer, and said second and third base layers, said second main electrode being in contact with said third base layer in the bottom and/or the side wall of said groove and in contact with said second base layer and said emitter layer or source layer in the side wall of said groove.

A method of fabricating a semiconductor element, comprising the steps of:

• forming a second base layer of a second conductivity type in one surface region of a first base layer of a first conductivity type such that the impurity concentration is constant in the depth direction of said second base layer;
• selectively forming an emitter layer or source layer of the first conductivity type in a surface region of said second base layer;
• forming a gate electrode on the surface of that region of said second base layer which is positioned between said emitter layer or source layer and said first base layer with a gate insulating film interposed between said gate electrode and said second base layer;
• selectively forming a collector layer or drain layer on the other surface region of said first base layer or on one surface region of said first base layer;
• and
• forming a first main electrode in contact with said collector layer or drain layer and a second main electrode in contact with said emitter layer or drain layer and said second base layer.