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US 2001/0026496 A1Published application
Semiconductor memory device allowing increase in capacity and operation speed with a suppressed layout area
AssigneeMitsubishi Denki Kabushiki Kaisha
InventorHIDETO HIDAKA
Life of this patent
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Abstract
A column select gate of a semiconductor memory device includes read gate circuits. Each read gate circuit includes read gate transistors. Each read gate transistor connects a read column select line to a global I/O line pair in response to a potential level on a bit line pair received on its gate and the potential on the read column select line. A voltage drop caused on one of the paired global I/O lines by turn-on of the read gate transistor is amplified by a main read amplifier to obtain read data.
Claims20
A semiconductor memory device for reading and writing storage data in accordance with an address signal, comprising:
- a plurality of memory cell blocks arranged in a matrix of a first number of columns and a second number of rows,
- each of said memory cell blocks including
- a plurality of memory cells arranged in a matrix of memory cell rows and memory cell columns,
- bit line pairs arranged corresponding to said memory cell columns, respectively, and
- at least one first data line pair for transmitting read data from one of said memory cells selected according to said address signal;
- a plurality of read column select lines for instructing selection of at least one of said memory cell columns;
- a column select circuit for selectively activating at least one of said read column select lines in accordance with said address signal;
- and
- a plurality of read data transmitting circuits, provided corresponding to said memory cell blocks, respectively, for transmitting said read data sent from the selected memory cell column onto said first data line pair,
- each of said read data transmitting circuits including
- a plurality of first gate circuits provided correspondingly to said memory cell columns, respectively, and each being activated by the corresponding one among said read column select lines,
- each of said first gate circuits having
- a first read gate switch for connecting the corresponding read column select line to one line of said first data line pair in accordance with the potential level on one of said paired bit lines, and
- a second read gate switch for connecting the corresponding read column select line to the other line of said first data line pair in accordance with the potential level on the other of said paired bit lines.
11 more elements
A semiconductor memory device for reading and writing storage data in accordance with an address signal, comprising:
- a plurality of memory cell blocks arranged in a matrix of a first number of columns and a second number of rows,
- each of said memory cell blocks including
- a plurality of memory cells arranged in a matrix of memory cell rows and memory cell columns, and
- bit line pairs arranged correspondingly to said memory cell columns, respectively;
- a plurality of read column select lines for instructing selection of one of said memory cell columns;
- a column select circuit for selectively activating at least one of said read column select lines in accordance with said address signal;
- a plurality of global data line pairs each provided in common for the second number of said memory cell blocks belonging to one same column of the memory cell blocks,
- a plurality of read data transmitting circuits, provided corresponding to said memory cell blocks, respectively, for transmitting said read data sent from the selected memory cell column onto said global data line pair,
- each of said read data transmitting circuits including a third number of first gate circuits each provided for each of said memory cell columns in each of said memory cell blocks,
- each of said first gate circuits being activated by a corresponding one of said read column select lines and having
- a first read gate switch for connecting said corresponding one of said read column select lines to a first one out of the remainder of said read column select lines in accordance with the potential level on one line of said bit line pair, and
- a second read gate switch for connecting said corresponding one of read column select lines to a second one out of the remainder of said read column select lines in accordance with the potential level on the other line of said bit line pair;
- and
- a plurality of column select line switching circuits each for connecting said first and second ones of said read column select lines to the lines of said global data line pair, respectively, in accordance with an instruction from said column select circuit.
11 more elements
A semiconductor memory device for reading and writing storage data in accordance with an address signal, comprising:
- a regular memory cell array having a plurality of regular memory cells arranged in rows and columns,
- said regular memory cell array being divided into a plurality of regular memory cell groups each having memory cell rows of M in number (M:
- natural number) and memory cell columns of N in number (N:
- natural number) being in correspondence with each other;
- and
- a redundant repair circuit for repairing a regular memory cell possibly having a defect,
- said redundant repair circuit including
- a plurality of spare memory cell groups to be replaced with the regular memory cell groups when said address signal matches with a replacement address,
- each of said spare memory cell groups including M spare memory cell rows and N spare memory cell columns,
- a plurality of replacement address storage circuits provided for the spare memory cell groups for storing, as said replacement addresses, the addresses corresponding to the regular memory cell groups containing the defective memory cells, respectively, and
- an address comparing circuit for instructing repairing of the regular memory cell in accordance with the comparison between said address signal and said replacement address.
8 more elements
Dependencies are inferred from the claim text.